M
2.4GHz 802.11b Zero-IF Transceivers
18
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Applications Information
Receive Path
LNA
The MAX2820/MAX2821 RX_RF inputs are high-
impedance RF differential inputs AC-coupled on-chip
to the LNA. The LNA inputs require external impedance
matching and differential to single-ended conversion.
The balanced to single-ended conversion and interface
to 50
is achieved through the use of an off-chip 2:1
balun transformer, such as the small surface-mount
baluns offered by Murata and Toko. In the case of the
2:1 balun, the RX RF input must be impedance-
matched to a differential/balanced impedance of 100
.
A simple LC network is sufficient to impedance-match
the LNA to the balun. The
Typical Application Circuit
shows the balun, inductors, and capacitors that consti-
tute the matching network. Refer to the MAX2820/
MAX2821 EV kit schematic for component values of the
matching network.
The line lengths and parasitics have a noticeable impact
on the matching element values in the board-level circuit.
Some empirical adjustment of LC component values is
likely. Balanced line layout on the differential input traces
is essential to maintaining good IP2 performance and RF
common-mode noise rejection.
The MAX2820/MAX2821 have two LNA gain modes that
are digitally controlled by the logic signal applied to
RF_GAIN. RF_GAIN high enables the high-gain mode,
and RF_GAIN low enables the low-gain mode. The LNA
gain step is nominally 30dB. In most applications,
RF_GAIN is connected directly to a CMOS output of the
baseband IC, and the baseband IC controls the state of
the LNA gain based on the detected signal amplitude.
Receiver Baseband Lowpass Filtering
The MAX2820/MAX2821 on-chip receive lowpass filters
provide the steep filtering necessary to attenuate the
out-of-band (> 11MHz) interfering signals to sufficiently
low levels to preserve receiver sensitivity. The filter fre-
quency response is precisely controlled on-chip and
does not require user adjustment. However, a provision
is made to permit the -3dB corner frequency and entire
response to be slightly shifted up or down in frequency.
This is intended to offer some flexibility in trading off
adjacent channel rejection vs. passband distortion. The
filter -3dB frequency is programmed through the serial
interface. The specific bit setting vs. -3dB frequency is
shown in Table 7. The typical receive baseband filter
gain vs. frequency profile is shown in the
Typical
Operating Characteristics
.
ADDRESS
DATA BIT
D11:D8
CONTENT
X
DEFAULT
0000
DESCRIPTION
Reserved
Phase-Detector Polarity Select
0 = No phase inversion
1 = Not permitted
Charge-Pump Current Select
0 =
±
1mA charge-pump current
1 =
±
2mA charge-pump current
Reference Frequency Divider
000000 = 22MHz
000001 = 44MHz
D7
PD
0
D6
ICP
1
0 0 1 0
D5:D0
R(5:0)
000000
Table 5. Synthesizer Register (SYNTH)
ADDRESS
DATA BIT
D11:D7
CONTENT
X
DEFAULT
00000
DESCRIPTION
Reserved
0 0 1 1
D6:D0
CF(6:0)
0100101
Channel Frequency Select: f
LO
= (2400 + CF(6:0))MHz
0000000 = 2400MHz
0000001 = 2401MHz
…………
1100010 = 2498MHz
1100011 = 2499MHz
Table 6. Channel Frequency Block Register (CHANNEL)