Complete Dual-Band
Quadrature Transmitter
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Pin Description
VGC
V
CC
IFOUT+,
IFOUT-
V
CC
RF and IF Variable-Gain Control Analog Input. VGC floats to +1.5V. Apply
+0.5V to +2.6V to control the gain of the RF and IF stages. An RC filter on this pin may be used
to reduce DAC noise or PDM clock spurs from this line.
20
Supply Pin for the IF VGA. Bypass with a capacitor as close to the pin as possible. The bypass
capacitor must not share its ground vias with any other branches.
21
Differential IF Outputs. These pins must be inductively pulled up to V
CC
. A differential IF band-
pass filter is connected between this port and IFIN+ and IFIN-. The pullup inductors can be part
of the filter structure. The differential output impedance of this port is nominally 600&. The trans-
mission lines from these pins should be short to minimize the pickup of spurious signals and
noise.
18, 19
Power supply. Bypass to ground with a 1000pF capacitor.
16, 17
PIN
NAME
FUNCTION
1
RFL
Transmitter RF Output for Cellular Band (800MHz to 1000MHz)for both FM and digital modes.
This open-collector output requires a pullup inductor to the supply voltage, which is part of the
output matching network and may be connected directly to the battery.
2
RFH
Transmitter RF Output for PCS Band (1700MHz to 2000MHz). This open collector output
requires a pullup inductor to the supply voltage. The pullup inductor is part of the output match-
ing network and may be connected directly to the battery.
Open-Collector Output Indicating Lock Status of the IF PLL. Requires a pullup resistor. Control
using configuration register bit LD_MODE.
LOCK
3
4
V
CC
Power Supply. Supply pin for the driver stage. V
CC
must be bypassed to system ground as
close to the pin as possible. The ground vias for the bypass capacitor should not be shared by
any other branch. Bypass to ground with 100pF and 100nF capacitors.
Power Supply. Connect to pin 4 for normal operation.
V
CC
5
6
V
CC
Supply Pin for the Upconverter Stage. V
CC
must be bypassed to system ground as close to the
pin as possible. The ground vias for the bypass capacitor should not be shared by any other
branch.
Digital Input. A logic low on TXGATE shuts down everything except the IF PLL, IF VCO, and ser-
ial bus and registers. This mode is used for IF PLL settling before the transmit time slot.
TXGATE
7
8, 9
IFIN+, IFIN-
Differential Inputs to the RF Upconverter. These pins are internally biased to +1.5V. The input
impedance for these ports is nominally 400& differential. The IF filter should be AC-coupled to
these ports. Keep the differential lines as short as possible to minimize stray pickup and shunt
capacitance.
No Connection. Leave these pins floating.
N.C.
10, 11
12
R
BIAS
Bias Resistor Pin. RBIAS is internally biased to a bandgap voltage of +1.18V. An external resistor
or current source must be connected to this pin to set the bias current for the upconverters and PA
driver stages. The nominal resistor value is 16k&. This value can be altered to optimize the linearity
of the driver stage.
Input Pins from the 3-Wire Serial Bus (SPI/QSPI/MICROWIRE compatible).
An R-C filter on each of these pins may be used to reduce noise.
CLK, DI, CS
13, 14, 15