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參數(shù)資料
| 型號： | MAX2365ETM+T |
| 廠商： | Maxim Integrated |
| 文件頁數(shù)： | 14/29頁 |
| 文件大?。?/td> | 460K |
| 描述： | IC TRANSMITTER QUAD 48TQFN-EP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,500 |
| 頻率： | 900MHz |
| 應(yīng)用： | 無線 LAN |
| 功率 - 輸出： | 9dBm |
| 電流 - 傳輸： | 90mA |
| 數(shù)據(jù)接口： | PCB，表面貼裝 |
| 天線連接器： | PCB，表面貼裝 |
| 電源電壓： | 2.7V ~ 3.3V |
| 工作溫度： | -40°C ~ 85°C |
| 封裝/外殼： | 48-WFQFN 裸露焊盤 |
| 包裝： | 帶卷 (TR) |
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Complete Dual-Band
Quadrature Transmitters
14 ______________________________________________________________________________________
Cascaded Performance
Tables 11 and 12 show the typical cascaded perfor-
mance for TDMA and W-CDMA systems.
3-Wire Interface
Figure 5 shows the 3-wire interface timing diagram. The
3-wire bus is SPI/QSPI/MICROWIRE compatible.
Electromagnetic
Compliance Considerations
Two major concepts should be employed to produce a
low-spur and EMC-compliant transmitter: minimize cir-
cular current-loop area to reduce H-field radiation. To
minimize circular current-loop area, bypass as close to
the part as possible and use the distributed capaci-
tance of a ground plane. To minimize voltage drops,
make V
CC
traces short and wide, and make RF traces
short.
Program only the necessary bits in any register to mini-
mize clock cycles. RC filtering can also be used to slow
the clock edges on the 3-wire interface, reducing high-
frequency spectral content. RC filtering also provides
for transient protection against IEC802 testing by shunt-
ing high frequencies to ground, while the series resis-
tance attenuates the transients for error-free operation.
The same applies to the logic input pins (SHDN,
TXGATE, IDLE).
Figure 1. Register Configuration
MSB
24 BIT REGISTER
LSB
DATA 20 BITS
ADDRESS 4 BITS
B18
B16
B19
B17
B14
B12
B15
B13
B10
B8
B11
B9
B6
B4
B7
B5
B2
B0
B3
B1
A2
A0
A3
A1
RFM DIVIDE RATIO (18)
ADDRESS
X
B16
X
B17
B14
B12
B15
B13
B10
B8
B11
B9
B6
B4
B7
B5
B2
B0
B3
B1
0
0
0
0
RFM DIVIDE REGISTER
RFR DIVIDE RATIO (13)
ADDRESS
X
X
X
X
X
B12
X
X
B10
B8
B11
B9
B6
B4
B7
B5
B2
B0
B3
B1
0
1
0
0
RFR DIVIDE REGISTER
IFM DIVIDE RATIO (14)
ADDRESS
X
X
X
X
X
B12
X
B13
B10
B8
B11
B9
B6
B4
B7
B5
B2
B0
B3
B1
0
0
0
1
IFM DIVIDE REGISTER
IFR DIVIDE RATIO (11)
ADDRESS
X
X
X
X
X
X
X
X
B10
B8
X
B9
B6
B4
B7
B5
B2
B0
B3
B1
0
1
0
1
IFR DIVIDE REGISTER
OPERATION CONTROL BITS (16)
ADDRESS
X
X
X
X
B14
B12
B15
B13
B10
B8
B11
B9
B6
B4
B7
B5
B2
B0
B3
B1
1
0
0
0
CONTROL REGISTER
CONFIGURATION BITS (16)
ADDRESS
X
X
X
X
B14
B12
B15
B13
B10
B8
B11
B9
B6
B4
B7
B5
B2
B0
B3
B1
1
1
0
0
CONFIGURATION REGISTER
TEST REGISTER
CURRENT CONTROL REGISTER
X = DONT CARE
1
0
1
1
B1
B3
B0
B2
B5
B7
B4
B6
X
X
B8
X
X
X
X
X
X
X
X
X
ADDRESS
1
0
0
1
B1
B3
B0
B2
B5
B7
B4
B6
B9
B11
B8
B10
B13
B12
B15
X
X
X
X
ADDRESS
CURRENT CONTROL BITS (16)
B14
TEST BITS (9)
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