參數(shù)資料
型號: MAX2362ECM
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 無繩電話/電話
英文描述: Quadruple Bus Buffer Gates With 3-State Outputs 14-SO -40 to 85
中文描述: TELECOM, CELLULAR, RF AND BASEBAND CIRCUIT, PQFP48
封裝: 7 X 7 MM, 1 MM HEIGHT, EXPOSED PAD, TQFP-48
文件頁數(shù): 20/24頁
文件大?。?/td> 413K
代理商: MAX2362ECM
M
Complete Dual-Band
Quadrature Transmitters
20
______________________________________________________________________________________
IF Tank Design
The low-band tank (TANKL+, TANKL-) and high-band
tank (TANKH+, TANKH-) are fully differential. The exter-
nal tank components are shown in Figure 6. The fre-
quency of oscillation is determined by the following
equation:
f
2
(C
INT
+
π
C
INT
= Internal capacitance of TANK port
C
D
= Capacitance of varactor
C
VAR
= Equivalent variable tuning capacitance
C
PAR
= Parasitic capacitance due to PCB pads and
traces
C
CENT
= External capacitor for centering oscillation fre-
quency
C
C
= External coupling capacitor to the varactor
Internal to the IC, the charge pump will have a leakage
of less than 10nA. This is equivalent to a 300M
shunt
resistor. The charge-pump output must see an
extremely high DC resistance of greater than 300M
.
This will minimize charge-pump spurs at the compari-
son frequency. Make sure there is no solder flux under
the varactor or loop filter.
Layout Issues
The MAX2360/MAX2362/MAX2364 EV kit can be used
as a starting point for layout. For best performance,
take into consideration power-supply issues as well as
the RF, LO, and IF layout.
Power-Supply Layout
To minimize coupling between different sections of the
IC, the ideal power-supply layout is a star configuration,
which has a large decoupling capacitor at a central
V
CC
node. The V
CC
traces branch out from this node,
each going to a separate V
CC
node in the MAX2360/
MAX2362/MAX2364 circuit. At the end of each trace is
a bypass capacitor with impedance to ground less than
1
at the frequency of interest. This arrangement pro-
vides local decoupling at each V
CC
pin. Use at least
one via per bypass capacitor for a low-inductance
ground connection.
Matching Network Layout
The layout of a matching network can be very sensitive
to parasitic circuit elements. To minimize parasitic
inductance, keep all traces short and place compo-
nents as close to the IC as possible. To minimize para-
sitic capacitance, a cutout in the ground plane (and
C
C
C
C
C
C
2 (C
+ C )
OSC
CENT
VAR
P
VAR
D
C
D
+
=
+
=
×
1
t
CS
t
CH
t
CWL
t
CWH
DI
CLK
CS
t
ES
B19 (MSB)
B18
B0
A3
A1
A0 (LSB)
t
CS
> 50ns
t
CH
> 10ns
t
CWH
> 50ns
t
ES
> 50ns
t
CWL
> 50ns
t
EW
> 50ns
t
EW
Figure 5. 3-Wire Interface Diagram
L
C
D
C
CENT
C
PAR
C
C
C
C
C
D
MAX2360
MAX2362
MAX2364
C
INT
-R
n
Figure 6. Tank Port Oscillator
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