參數(shù)資料
型號(hào): MAX19713ETN+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 12/37頁(yè)
文件大?。?/td> 0K
描述: IC ANLG FRNT END 56-TQFN
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 2,500
位數(shù): 10
通道數(shù): 2
功率(瓦特): 91.8mW
電壓 - 電源,模擬: 3V
電壓 - 電源,數(shù)字: 3V
封裝/外殼: 56-WFQFN 裸露焊盤(pán)
供應(yīng)商設(shè)備封裝: 56-TQFN-EP(7x7)
包裝: 帶卷 (TR)
MAX19713
10-Bit, 45Msps, Full-Duplex
Analog Front-End
2
_______________________________________________________________________________________
ABSOLUTE MAXIMUM RATINGS
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to
absolute maximum rating conditions for extended periods may affect device reliability.
VDD to GND, OVDD to OGND ..............................-0.3V to +3.6V
GND to OGND.......................................................-0.3V to +0.3V
IAP, IAN, QAP, QAN, IDP, IDN, QDP,
QDN, DAC1, DAC2, DAC3 to GND .....................-0.3V to VDD
ADC1, ADC2 to GND.................................-0.3V to (VDD + 0.3V)
REFP, REFN, REFIN, COM to GND ...........-0.3V to (VDD + 0.3V)
AD0–AD9, DA0–DA9, SCLK, DIN,
CS/WAKE,
CLK, DOUT to OGND .........................-0.3V to (OVDD + 0.3V)
Continuous Power Dissipation (TA = +70°C)
56-Pin Thin QFN-EP (derate 27.8mW/°C above +70°C) 2.22W
Thermal Resistance
θJA ..................................................36°C/W
Operating Temperature Range ...........................-40°C to +85°C
Junction Temperature ......................................................+150°C
Storage Temperature Range .............................-60°C to +150°C
Lead Temperature (soldering, 10s) .................................+300°C
ELECTRICAL CHARACTERISTICS
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL
≈ 10pF on all digital outputs, fCLK = 45MHz (50% duty cycle), Rx ADC input amplitude
= -0.5dBFS, Tx DAC output amplitude = 0dBFS, CM1 = 0, CM0 = 0, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33F, CL < 5pF on all aux-DAC outputs, TA = TMIN to TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage
VDD
2.7
3.0
3.3
V
Output Supply Voltage
OVDD
1.8
VDD
V
FD mode: fCLK = 45MHz, fOUT = 2.2MHz on
both DAC channels;
fIN = 5.5MHz on both ADC channels; aux-
DACs ON and at midscale, aux-ADC ON
31.9
37
SPI2-Tx mode: fCLK = 45MHz, fOUT =
2.2MHz on both DAC channels; Rx ADC
OFF; aux-DACs ON and at midscale, aux-
ADC ON
16.7
19
SPI1-Rx mode: fCLK = 45MHz, fIN =
5.5MHz on both ADC channels; Tx DAC
OFF (Tx DAC outputs at 0V); aux-DACs
ON and at midscale, aux-ADC ON
27.6
32
SPI4-Tx mode: fCLK = 45MHz, fOUT =
2.2MHz on both DAC channels; Rx ADC
ON (output tri-stated); aux-DACs ON and
at midscale, aux-ADC ON
31.0
36
SPI3-Rx mode: fCLK = 45MHz, fIN =
5.5MHz on both channels; Tx DAC ON (Tx
DAC outputs at midscale); aux-DACs ON
and at midscale, aux-ADC ON
30.2
35
VDD Supply Current
Standby mode: CLK = 0 or OVDD;
aux-DACs ON and at midscale,
aux-ADC ON
3.3
5
mA
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