參數(shù)資料
型號： MAX19707ETM
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
中文描述： SPECIALTY TELECOM CIRCUIT, QCC48
封裝： 7 X 7 MM, 0.80 MM HEIGHT, MO-220, TQFN-48
文件頁數(shù)： 7/37頁
文件大?。?/td> 561K
代理商： MAX19707ETM
M
10-Bit, 45Msps, Ultra-Low-Power
Analog Front-End
_______________________________________________________________________________________
7
ELECTRICAL CHARACTERISTICS (continued)
(V
DD
= 3V, OV
DD
= 1.8V, internal reference (1.024V), C
L
≈
10pF on all digital outputs, f
CLK
= 45MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, C
REFP
= C
REFN
=
C
COM
= 0.33μF, unless otherwise noted. C
L
< 5pF on all aux-DAC outputs. Typical values are at T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Q-DAC DATA to CLK Rise Setup
Time
t
DSQ
Figure 5 (Note 6)
9
ns
CLK Fall to I-DAC Data Hold Time
t
DHI
Figure 5 (Note 6)
-4
ns
CLK Rise to Q-DAC Data Hold
Time
t
DHQ
Figure 5 (Note 6)
-4
ns
CLK Duty Cycle
CLK Duty-Cycle Variation
Digital Output Rise/Fall Time
SERIAL-INTERFACE TIMING CHARACTERISTICS (Figure 6, Note 6)
50
±15
2.6
%
%
ns
20% to 80%
Falling Edge of
CS
to Rising Edge
of First SCLK Time
t
CSS
10
ns
DIN to SCLK Setup Time
DIN to SCLK Hold Time
SCLK Pulse-Width High
SCLK Pulse-Width Low
SCLK Period
SCLK to
CS
Setup Time
CS
High Pulse Width
CS
High to DOUT Active High
t
DS
t
DH
t
CH
t
CL
t
CP
t
CS
t
CSW
t
CSD
10
0
25
25
50
10
80
ns
ns
ns
ns
ns
ns
ns
ns
Bit AD0 set
200
CS
High to DOUT Low (Aux-ADC
Conversion Time)
t
CONV
Bit AD0 set, no averaging (see Table 14),
f
CLK
= 45MHz,
CLK divider = 16 (see Table 15)
4.27
μs
DOUT Low to
CS
Setup Time
SCLK Low to DOUT Data Out
CS
High to DOUT High Impedance
MODE-RECOVERY TIMING CHARACTERISTICS (Figure 7)
t
DCS
t
CD
t
CHZ
Bit AD0, AD10 set
Bit AD0, AD10 set
Bit AD0, AD10 set
200
ns
ns
ns
14.5
200
From shutdown to Rx mode, ADC settles
to within 1dB SINAD
85.2
Shutdown Wake-Up Time
t
WAKE,SD
From shutdown to Tx mode, DAC settles to
within 10 LSB error
28.2
μs
Fr om i d e to Rx m od e w h C LK p esent
d ur ng i d e, AD C settl es to w hi n 1d B S N AD
9.8
Idle Wake-Up Time (With CLK)
t
WAKE,ST0
From idle to Tx mode with CLK present
during idle, DAC settles to 10 LSB error
6.4
μs
From standby to Rx mode, ADC settles to
within 1dB SINAD
13.7
Standby Wake-Up Time
t
WAKE,ST1
From standby to Tx mode, DAC settles to
10 LSB error
24
μs
相關(guān)PDF資料
PDF描述
MAX19708 10-Bit, 45Msps, Ultra-Low-Power Analog Front-End
MAX1971EEE Fixed-Point Digital Signal Processor 532-FCBGA
MAX1970-MAX1972 Dual, 180∑ Out-of-Phase, 1.4MHz, 750mA Step- Down Regulator with POR and RSI/PFO
MAX1970 Dual, 180∑ Out-of-Phase, 1.4MHz, 750mA Step- Down Regulator with POR and RSI/PFO
MAX1970EEE Fixed-Point Digital Signal Processor 532-FCBGA
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX19707ETM+ 功能描述:ADC / DAC多通道 45Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19707ETM+T 功能描述:ADC / DAC多通道 45Msps CODEC/AFE 1.8/2.7-3.3V RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19707ETM-T 功能描述:ADC / DAC多通道 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19707EVCMOD2 功能描述:ADC / DAC多通道 Evaluation System for the MAX19707 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
MAX19707EVCMODU 功能描述:ADC / DAC多通道 Evaluation System for the MAX19707 RoHS:否 制造商:Texas Instruments 轉(zhuǎn)換速率: 分辨率:8 bit 接口類型:SPI 電壓參考: 電源電壓-最大:3.6 V 電源電壓-最小:2 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-40
發(fā)布緊急采購，3分鐘左右您將得到回復。

采購需求

(若只采購一條型號，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

發(fā)布成功！您可以繼續(xù)發(fā)布采購。也可以進入我的后臺，查看報價

*型號 *數(shù)量 廠商 批號 封裝
添加更多采購

我的聯(lián)系方式

*
*
*