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MAX19705
10-Bit, 7.5Msps, Ultra-Low-Power
Analog Front-End
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9
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL
≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33F, unless otherwise noted. CL < 5pF on all aux-DAC outputs. Typical values are at TA = +25°C.) (Note 1)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DIGITAL INPUTS (CLK, SCLK, DIN,
CS, D0–D9, T/R, SHDN)
Input High Threshold
VINH
0.7 x OVDD
V
Input Low Threshold
VINL
0.3 x OVDD
V
Input Leakage
DIIN
D0–D9, CLK, SCLK, DIN,
CS, T/R,
SHDN = OGND or OVDD
-1
+1
A
Input Capacitance
DCIN
5pF
DIGITAL OUTPUTS (D0–D9, DOUT)
Output-Voltage Low
VOL
ISINK = 200A
0.2 x OVDD
V
Output-Voltage High
VOH
ISOURCE = 200A
0.8 x OVDD
V
Tri-State Leakage Current
ILEAK
-1
+1
A
Tri-State Output Capacitance
COUT
5pF
Note 1: Specifications from TA = +25°C to +85°C are guaranteed by production tests. Specifications from TA = +25°C to -40°C are
guaranteed by design and characterization.
Note 2: Guaranteed by design and characterization.
Note 3: The minimum clock frequency (fCLK) for the MAX19705 is 1.5MHz (typ). The minimum aux-ADC sample rate clock frequency
(ACLK) is determined by fCLK and the chosen aux-ADC clock-divider value. The minimum aux-ADC ACLK > 1.5MHz / 128
= 11.7kHz. The aux-ADC conversion time does not include the time to clock the serial data out of the SPI. The maximum
conversion time (for no averaging, NAVG = 1) will be tCONV (max) = (12 x 1 x 128) / 1.5MHz = 1024s.
Note 4: SNR, SINAD, SFDR, HD3, and THD are based on a differential analog input voltage of -0.5dBFS referenced to the amplitude
of the digital outputs. SINAD and THD are calculated using HD2 through HD6.
Note 5: Crosstalk rejection is measured by applying a high-frequency test tone to one channel and a low-frequency tone to the second
channel. FFTs are performed on each channel. The parameter is specified as the power ratio of the first and second channel
FFT test tone.
Note 6: Amplitude and phase matching is measured by applying the same signal to each channel, and comparing the two output
signals using a sine-wave fit.
Typical Operating Characteristics
(VDD = 3V, OVDD = 1.8V, internal reference (1.024V), CL
≈ 10pF on all digital outputs, fCLK = 7.5MHz (50% duty cycle), Rx ADC input
amplitude = -0.5dBFS, Tx DAC output amplitude = 0dBFS, differential Rx ADC input, differential Tx DAC output, CREFP = CREFN =
CCOM = 0.33F, TA = +25°C, unless otherwise noted.)
Rx ADC CHANNEL-IA FFT PLOT
MAX19705
toc01
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
3.0
2.0
1.0
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
0
3.5
2.5
1.5
0.5
fCLK = 7.5MHz
fIA = 1.8063354MHz
AIA = -0.561dB
8192-POINT
DATA RECORD
4
3
6
2
7
10
8
9
5
Rx ADC CHANNEL-QA FFT PLOT
MAX19705
toc02
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
fCLK = 7.5MHz
fQA = 1.8063354MHz
AQA = -0.533dB
8192-POINT
DATA RECORD
3.0
2.0
1.0
0
3.5
2.5
1.5
0.5
4
3 7
2
6
10
8
9
5
Rx ADC CHANNEL-IA
TWO-TONE FFT PLOT
MAX19705
toc05
FREQUENCY (MHz)
AMPLITUDE
(dBFS)
-90
-80
-70
-60
-50
-40
-30
-20
-10
0
-100
fCLK = 7.5MHz
f1 = 2.0MHz
f2 = 2.1MHz
AIA = -7dBFS
PER TONE
8192-POINT
DATA RECORD
3.0
2.0
1.0
0
3.5
2.5
1.5
0.5
f1
f2