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參數(shù)資料
| 型號： | MAX195BEWE+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/28頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 16BIT 85KSPS 16-SOIC |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 1,000 |
| 位數(shù)： | 16 |
| 采樣率（每秒）： | 85k |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉換器數(shù)目： | 2 |
| 功率耗散（最大）： | 80mW |
| 電壓電源： | 模擬和數(shù)字，雙 ± |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 16-SOIC（0.295"，7.50mm 寬） |
| 供應商設備封裝： | 16-SOIC W |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 1 個單端，單極；1 個單端，雙極 |
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MAX195
An OR gate is used to synchronize the “start” signal to
the asynchronous CLK, as described in the
External
Clock section. As with Mode 1, the QSPI processor must
run CLK during calibration and either count CLK cycles
or, as is done here, monitor EOC to determine when cal-
ibration is complete. Also, EOC is polled by the P to
determine when a conversion result is available. When
EOC goes low, data is clocked out at the highest QSPI
data rate (4.19Mbps). After the data is transferred, a
new conversion can be initiated whenever desired.
The timing specification for SCLK-to-DOUT valid (tSD)
imposes some constraints on the serial interface. At
SCLK rates up to 2.5Mbps, data is clocked out of the
MAX195 by a falling edge of SCLK and may be
clocked into the P by the next rising edge (CPOL = 0,
CPHA = 0). For data rates greater than 2.5Mbps (or for
lower rates, if desired) it is necessary to clock data out
of the MAX195 on SCLK’s falling edge and to clock it
into the P on SCLK’s next falling edge (CPOL = 0,
CPHA = 1). Also, your processor hold time must not
exceed tSD minimum (20ns). As with CLK in mode 1,
maximum SCLK rates may not be possible with some
interface specifications that are subsets of SPI.
Supplies, Layout, Grounding
and Bypassing
For best system performance, use printed circuit
boards with separate analog and digital ground planes.
Wire-wrap boards are not recommended. The two
ground planes should be tied together at the low-
impedance power-supply source and at the MAX195
(Figure 22.) If the analog and digital supplies come
from the same source, isolate the digital supply from
the analog supply with a low-value resistor (10
).
Constraints on sequencing the four power supplies are
as follows.
Apply VDDA before VDDD.
Apply VSSA before VSSD.
Apply AIN and REF after VDDA and VSSA are present.
The power supplies should settle within the
MAX195’s power-on delay (minimum 500ns) or you
should recalibrate the converter (pulse RESET low)
before use.
16-Bit, 85ksps ADC with 10A Shutdown
18
______________________________________________________________________________________
CS
CLK
START
588ns
239ns
CONVERSION TIME
4.19MHz
1.3
s
9.4
s
17
s*
5.1
s
4
s
EOC
SCLK
DOUT
B15
B3 B2
B13
B14
B1
B0
* INTERRUPT LATENCY OF THE PROCESSOR
Figure 20. Timing Diagram for Circuit of Figure 19 (Mode 2)
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MAX195BMDE | 功能描述:模數(shù)轉換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX195EVC16-DIP | 功能描述:模數(shù)轉換器 - ADC Programmers, Development Systems RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結構:Sigma-Delta 轉換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX195EVKIT-DIP | 功能描述:數(shù)據(jù)轉換 IC 開發(fā)工具 Programmers, Development Systems RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類型:ADC 工具用于評估:ADS130E08 接口類型:SPI 工作電源電壓:- 6 V to + 6 V |
| MAX1960EEP | 功能描述:DC/DC 開關控制器 RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
| MAX1960EEP+ | 功能描述:DC/DC 開關控制器 1MHz PWM Step-Down RoHS:否 制造商:Texas Instruments 輸入電壓:6 V to 100 V 開關頻率: 輸出電壓:1.215 V to 80 V 輸出電流:3.5 A 輸出端數(shù)量:1 最大工作溫度:+ 125 C 安裝風格: 封裝 / 箱體:CPAK |
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