參數(shù)資料
型號(hào): MAX195BCWE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 16-Bit, 85ksps ADC with 10レA Shutdown
中文描述: 1-CH 16-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝: 0.300 INCH, PLASTIC, SOIC-16
文件頁數(shù): 18/28頁
文件大?。?/td> 311K
代理商: MAX195BCWE
M
An OR gate is used to synchronize the “start” signal to
the asynchronous CLK, as described in the External
Clock section. As with Mode 1, the QSPI processor must
run CLK during calibration and either count CLK cycles
or, as is done here, monitor
EOC
to determine when cal-
ibration is complete. Also,
EOC
is polled by the μP to
determine when a conversion result is available. When
EOC
goes low, data is clocked out at the highest QSPI
data rate (4.19Mbps). After the data is transferred, a
new conversion can be initiated whenever desired.
The timing specification for SCLK-to-DOUT valid (t
SD
)
imposes some constraints on the serial interface. At
SCLK rates up to 2.5Mbps, data is clocked out of the
MAX195 by a falling edge of SCLK and may be
clocked into the μP by the next rising edge (CPOL = 0,
CPHA = 0). For data rates greater than 2.5Mbps (or for
lower rates, if desired) it is necessary to clock data out
of the MAX195 on SCLK’s falling edge and to clock it
into the μP on SCLK’s next falling edge (CPOL = 0,
CPHA = 1). Also, your processor hold time must not
exceed t
SD
minimum (20ns). As with CLK in mode 1,
maximum SCLK rates may not be possible with some
interface specifications that are subsets of SPI.
S upplies, Layout, Grounding
and Bypassing
For best system performance, use printed circuit
boards with separate analog and digital ground planes.
Wire-wrap boards are not recommended. The two
ground planes should be tied together at the low-
impedance power-supply source and at the MAX195
(Figure 22.) If the analog and digital supplies come
from the same source, isolate the digital supply from
the analog supply with a low-value resistor (10
).
Constraints on sequencing the four power supplies are
as follows.
Apply VDDA before VDDD.
Apply VSSA before VSSD.
Apply AIN and REF after VDDA and VSSA are present.
The power supplies should settle within the
MAX195’s power-on delay (minimum 500ns) or you
should recalibrate the converter (pulse
RESET
low)
before use.
16-Bit, 85ksps ADC with 10μA S hutdown
18
______________________________________________________________________________________
CS
CLK
START
588ns
239ns
CONVERSION TIME
9.4
μ
s
4.19MHz
1.3
μ
s
17
μ
s*
5.1
μ
s
4
μ
s
EOC
SCLK
DOUT
B15
B3 B2
B13
B14
B1
B0
* INTERRUPT LATENCY OF THE PROCESSOR
Figure 20. Timing Diagram for Circuit of Figure 19 (Mode 2)
相關(guān)PDF資料
PDF描述
MAX195BCPE 16-Bit, 85ksps ADC with 10レA Shutdown
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MAX195BCWE+ 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 85ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX195BCWE+T 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 16-Bit 85ksps 5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
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