參數(shù)資料
型號: MAX19527EXE+
廠商: Maxim Integrated Products
文件頁數(shù): 19/30頁
文件大?。?/td> 0K
描述: IC ADC 12BIT 8CH 50MSPS 144CTBGA
應用說明: Ultrasound Imaging Systems Application Note
產品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 240
位數(shù): 12
采樣率(每秒): 50M
數(shù)據(jù)接口: 串行,SPI?
轉換器數(shù)目: 8
功率耗散(最大): 2.96W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 144-TFBGA
供應商設備封裝: 144-CTFBGA
包裝: 管件
輸入數(shù)目和類型: 16 個單端,單極;8 個差分,單極
Ultra-Low-Power, Octal, 12-Bit, 50Msps,
1.8V ADC with Serial LVDS Outputs
MAX19527
26
Reserved Registers (0Ah to 0Fh)
These registers are reserved and should not be used or
programmed. It is possible to read from or write to these
registers, but the commands have no effect on device
operation.
Special Function Register (10h)
The Special Function register has two key functions: soft-
ware device reset and device status. To initiate a soft-
ware device reset, write the command 5Ah to the Special
Function register. Do not write any other values to this
register as they could permanently alter the device con-
figuration. When read, the register returns a status byte
with the information described in Table 24.
Applications Information
Analog Inputs
The ADC provides better SFDR and THD with fully
differential input signals than a single-ended input drive.
In differential input mode, even-order harmonics are
lower as both inputs are balanced, and each of the ADC
inputs only require half the signal swing compared to
single-ended input mode. Single-ended operation for the
device is not recommended.
AC-Coupled Inputs
An RF transformer provides an excellent solution for
converting a single-ended signal to a fully differential
signal (Figure 11). CMOUT provides the common-mode
voltage for an AC-coupled input. The transformer shown
has an impedance ratio of 1:1. Alternatively, a different
step-up transformer can be selected to reduce the drive
requirements. A reduced signal swing from the input
driver can also improve the overall distortion.
Clock Inputs
Differential, AC-Coupled Clock Inputs
For optimum dynamic performance, the clock inputs
to the device should be driven with an AC-coupled
differential signal. However, frequently the available
clock source is single-ended. Figure 12 demonstrates
one method for converting a single-ended clock sig-
nal into a differential signal with a transformer. In this
example, a Coilcraft transformer (TTWB-2-B), whose
impedance ratio from primary to secondary is 1:2.
The signal in this example is terminated into a series
combination of two 50
Ω resistors with their common node
AC-coupled to ground. Figure 12 illustrates the second-
ary side of the transformer to be coupled directly to the
clock inputs. Since the clock inputs are self-biasing,
the center tap of the transformer must be AC-coupled
to ground or left unconnected. If the center tap of the
transformer’s secondary side is DC-coupled to ground,
it is necessary to add blocking capacitors in series with
the clock inputs.
Clock jitter performance can be enhanced if the clock
signal has a high slew rate at the time of its zero-
crossing. Therefore, if a sinusoidal source is used to
drive the clock inputs, the clock amplitude should be
as large as possible to maximize the zero-crossing slew
rate. The back-to-back Schottky diodes shown in Figure
12 are not required as long as the input signal is held
to a differential voltage potential of 3VP-P or less. If a
larger amplitude signal is provided (to maximize the
zero-crossing slew rate), then the diodes serve to limit
the differential signal swing at the clock inputs.
Any differential mode noise coupled to the clock inputs
translates to clock jitter and degrades the SNR perfor-
mance of the device. Any differential mode coupling of
the analog input signal into the clock inputs results in
harmonic distortion. Consequently, it is important that the
clock lines be well isolated from the analog signal input
and from the digital outputs.
Table 23. Custom Test Pattern 3 (09h)
Table 24. Special Function Register (10h)
Status Byte (Read)
STATUS
BIT NO.
READ
VALUE
DESCRIPTION
7
0
Reserved
6
0
Reserved
5
0 or 1
1 = ROM read in progress
4
0 or 1
1 = ROM read completed, and
register data is valid (checksum ok)
3
0
Reserved
2
1
Reserved
1
0 or 1
Reserved
0
0 or 1
1 = Duty-cycle equalizer DLL is
locked
BIT 7
BIT 6
BIT 5
BIT 4
BIT 3
BIT 2
BIT 1
BIT 0
BITS_CUSTOM2[11:8]
BITS_CUSTOM1[11:8]
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