參數(shù)資料
型號: MAX189CEWE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: +5V, Low-Power, 12-Bit Serial ADCs
中文描述: 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO16
封裝: 0.300 INCH, SOP-16
文件頁數(shù): 15/20頁
文件大?。?/td> 177K
代理商: MAX189CEWE
____________Applic ations Information
Connec tion to S tandard Interfac es
The MAX187/MAX189 serial interface is fully compatible
with SPI, QSPI, and Microwire standard serial
interfaces.
If a serial interface is available, set the CPU’s serial
interface in master mode so the CPU generates the ser-
ial clock. Choose a clock frequency up to 2.5MHz.
1. Use a general-purpose I/O line on the CPU to pull
CS
low. Keep SCLK low.
2. Wait the for the maximum conversion time specified
before activating SCLK. Alternatively, look for a
DOUT rising edge to determine the end of
conversion.
3. Activate SCLK for a minimum of 13 clock cycles. The
first falling clock edge will produce the MSB of the
DOUT conversion. DOUT output data transitions on
SCLK’s falling edge and is available in MSB-first for-
mat. Observe the SCLK to DOUT valid timing charac-
teristic. Data can be clocked into the μP on SCLK’s
rising edge.
4. Pull
CS
high at or after the 13th falling clock edge. If
CS
remains low, trailing zeros are clocked out after
the LSB.
5. With
CS
= high, wait the minimum specified time, t
CS
,
before launching a new conversion by pulling
CS
low. If a conversion is aborted by pulling
CS
high
before the conversions end, wait for the minimum
acquisition time, t
AC Q
, before starting a new
conversion.
Data can be output in 1-byte chunks or continuously, as
shown in Figure 8. The bytes will contain the result of
the conversion padded with one leading 1, and trailing
0s if SCLK is still active with
CS
kept low.
M
+5V, Low-Power, 12-Bit S erial ADCs
______________________________________________________________________________________
15
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
HI-Z
tCONV
DOUT
CS
SCLK
HI-Z
1ST BYTE READ
2ND BYTE READ
EOC
MSB
D10
D9
D8
D7
D6
D5
D4
D3
D2
D1
LSB
HI-Z
tCONV
DHI-Z
CS
SCLK
EOC
Figure 14. SPI/Microwire Serial Interface Timing (CPOL = CPHA = 0)
Figure 15. QSPI Serial Interface Timing (CPOL = CPHA = 0)
相關(guān)PDF資料
PDF描述
MAX187CCWE +5V, Low-Power, 12-Bit Serial ADCs
MAX189CCWE +5V, Low-Power, 12-Bit Serial ADCs
MAX189CCPA +5V, Low-Power, 12-Bit Serial ADCs
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MAX189ACPA +5V, Low-Power, 12-Bit Serial ADCs
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