參數(shù)資料
型號(hào): MAX1854EEG
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): 穩(wěn)壓器
英文描述: High-Speed, Adjustable, Synchronous Step-Down Controllers with Integrated Voltage Positioning
中文描述: SWITCHING CONTROLLER, 550 kHz SWITCHING FREQ-MAX, PDSO24
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-24
文件頁(yè)數(shù): 24/33頁(yè)
文件大?。?/td> 840K
代理商: MAX1854EEG
M
High-Speed, Adjustable, Synchronous Step-Down
Controllers with Integrated Voltage Positioning
24
______________________________________________________________________________________
MOSFET Power Dissipation
Worst-case conduction losses occur at the duty factor
extremes. For the high-side MOSFET (Q1), the worst-
case power dissipation due to resistance occurs at the
minimum input voltage:
PD (Q1 Resistive) = (V
OUT
/V+)
×
I
LOAD
2
×
R
DS(ON)
Generally, a small high-side MOSFET is desired to
reduce switching losses at high input voltages.
However, the R
DS(ON)
required to stay within package
power-dissipation often limits how small the MOSFET
can be. Again, the optimum occurs when the switching
losses equal the conduction (R
DS(ON)
) losses. High-
side switching losses don
t usually become an issue
until the input is greater than approximately 15V.
Calculating the power dissipation in the high-side MOS-
FET (Q1) due to switching losses is difficult since it
must allow for difficult quantifying factors that influence
the turn-on and turn-off times. These factors include the
internal gate resistance, gate charge, threshold volt-
age, source inductance, and PC board layout charac-
teristics. The following switching-loss calculation
provides only a very rough estimate and is no substi-
tute for breadboard evaluation, preferably including
verification using a thermocouple mounted on Q1:
CRSSV(MAX)2fSWILOAD
=
where C
RSS
is the reverse transfer capacitance of Q1,
and I
GATE
is the peak gate-drive source/sink current
(1A typ).
Switching losses in the high-side MOSFET can become
an insidious heat problem when maximum AC adapter
voltages are applied, due to the squared term in the
C
×
V
2
×
SW
switching-loss equation. If the high-side
MOSFET chosen for adequate R
DS(ON)
at low battery
voltages becomes extraordinarily hot when biased from
V+
(MAX)
, consider choosing another MOSFET with
lower parasitic capacitance.
For the low-side MOSFET (Q2), the worst-case power
dissipation always occurs at maximum input voltage:
The worst case for MOSFET power dissipation occurs
under heavy overloads that are greater than
I
LOAD(MAX)
but are not quite high enough to exceed
the current limit and cause the fault latch to trip. To pro-
tect against this possibility,
overdesign
the circuit to
tolerate:
I
LOAD
= I
LIMIT(HIGH)
+ (I
LOAD(MAX)
×
LIR/2)
where I
LIMIT(HIGH)
is the maximum valley current
allowed by the current-limit circuit, including threshold
tolerance and on-resistance variation. The MOSFETs
must be very well heatsinked to handle the overload
power dissipation.
Choose a Schottky diode (D1) with a forward voltage
low enough to prevent the low-side MOSFET body
diode from turning on during the dead-time. As a gen-
eral rule, select a diode with a DC current rating equal
to 1/3 of the load current. This diode is optional and
can be removed if efficiency isn
t critical.
Setting Voltage Positioning (VPS)
Voltage positioning dynamically changes the output
voltage set point in response to the load current. When
the output is loaded, the signal fed back from the VPS
input adjusts the output voltage set point, thereby
decreasing power dissipation. The load transient
response of this control loop is extremely fast yet well
controlled, so the amount of voltage change can be
accurately confined within the limits stipulated in the
microprocessor power-supply guidelines. To under-
stand the benefits of dynamically adjusting the output
voltage, see
Voltage Positioning and Effective Efficiency
.
The amount of voltage change is set by a small-value
sense resistor (R
SENSE
). Place this resistor between the
source of the low-side MOSFET and PGND. The volt-
age developed across this resistor (V
VPS
) relates to the
output voltage as follows:
V
OUT
= V
OUT(PROG)
(1 + A
VPS
V
VPS
)
where V
OUT(PROG)
is the programmed output voltage
set by the DAC code (Table 5), and the voltage-posi-
tioning gain factor (A
VPS
) is 0.175%/mV (see
Electrical
Characteristics
). The MAX1716/MAX1854/MAX1855
contain internal clamps to limit the voltage positioning
between 10% below and 2% above the programmed
output voltage.
The voltage present at VPS can be set in several differ-
ent ways. Connect VPS directly to CS through a 1k
resistor, or through a resistive divider. When connected
directly to CS, the output voltage position is:
V
VPS
= V
CS
= -I
LOAD
R
SENSE
(1 - D)
where D = V
OUT
/ V+ is the regulator
s duty cycle.
However, since the ratio of the output to input voltage is
usually relatively large, the effect of the duty cycle on
the circuit
s performance is not significant. Therefore,
PD(Q2 RESISTIVE)
I
VOUT
V(MAX)
ILOAD
2
RDS(ON)
=
+
PD(Q1SWITCHING)
IGATE
+
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