M
2.7A, 1MHz, Low-Voltage, Step-Down Regulator with
Internal Synchronous Rectification in QFN Package
8
_______________________________________________________________________________________
Idle Mode
Under light loads, this device improves efficiency by
switching to a pulse-skipping idle mode. Idle-mode
operation occurs when the current through the PMOS
switch is less than the idle-mode threshold current. Idle
mode forces the PMOS to remain on until the current
through the switch reaches the idle mode threshold,
thus minimizing the unnecessary switching that
degrades efficiency under light loads. In idle mode, the
device operates in discontinuous conduction. Current-
sense circuitry monitors the current through the NMOS
synchronous switch, turning it off before the current
reverses. This prevents current from being pulled from
the output filter through the inductor and NMOS switch to
ground. As the device switches between operating
modes, no major shift in circuit behavior occurs.
100% Duty-Cycle Operation
When the input voltage drops near the output voltage,
the duty cycle increases until the PMOS MOSFET is on
continuously. The dropout voltage in 100% duty cycle
is the output current multiplied by the on-resistance of
the internal PMOS switch and parasitic resistance in the
inductor. The PMOS switch remains on continuously as
long as the current limit is not reached.
Shutdown
Drive
SHDN
to a logic-level low to place the MAX1843
in low-power shutdown mode and reduce supply cur-
rent to less than 1μA. In shutdown, all circuitry and
internal MOSFETs turn off, and the LX node becomes
high impedance. Drive
SHDN
to a logic-level high or
connect to V
CC
for normal operation.
Summing Comparator
Three signals are added together at the input of the
summing comparator
(Figure 2):
an output voltage error
signal relative to the reference voltage, an integrated
output voltage error correction signal, and the sensed
PMOS switch current. The integrated error signal is pro-
vided by a transconductance amplifier with an external
capacitor at COMP. This integrator provides high DC
accuracy without the need for a high-gain amplifier.
Connecting a capacitor at COMP modifies the overall
loop response (see the
Integrator Amplifier
section).
Synchronous Rectification
In a step-down regulator without synchronous rectifica-
tion, an external Schottky diode provides a path for cur-
rent to flow when the inductor is discharging. Replacing
the Schottky diode with a low-resistance NMOS syn-
chronous switch reduces conduction losses and
improves efficiency.
The NMOS synchronous-rectifier switch turns on follow-
ing a short delay after the PMOS power switch turns off,
thus preventing cross-conduction or
“
shoot through.
”
In
constant-off-time mode, the synchronous-rectifier switch
turns off just prior to the PMOS power switch turning on.
While both switches are off, inductor current flows
through the internal body diode of the NMOS switch. The
internal body diode
’
s forward voltage is relatively high.
Thermal Resistance
Junction-to-ambient thermal resistance,
θ
JA
, is highly
dependent on the amount of copper area immediately
surrounding the IC leads. The MAX1843 EV kit has 1in
2
of copper area and a thermal resistance of 50
°
C/W with
no forced airflow. Airflow over the board significantly
reduces the junction-to-ambient thermal resistance. For
heatsinking purposes, it is essential to connect the
exposed backside pad to a large analog ground plane.
Power Dissipation
Power dissipation in the MAX1843 is dominated by
conduction losses in the two internal power switches.
Power dissipation due to supply current in the control
section and average current used to charge and dis-
charge the gate capacitance of the internal switches
(i.e., switching losses) is approximately:
P
DS
= C x V
IN2
x f
PWM
where C = 2.5nF and f
PWM
is the switching frequen-
cy in PWM mode.
This number is reduced when the switching frequency
decreases as the part enters idle mode. Combined con-
duction losses in the two power switches are approxi-
mated by:
P
D
= I
OUT2
x R
PMOS
where R
PMOS
is the on-resistance of the PMOS switch.
The junction-to-ambient thermal resistance required to
dissipate this amount of power is calculated by:
θ
JA
= (T
J,MAX
- T
A,MAX
) / P
D(T
OT
)
where:
θ
JA
= junction-to-ambient thermal resistance
T
J(MAX)
= maximum junction temperature
T
A(MAX)
= maximum ambient temperature
P
D(TOT)
= total losses