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參數(shù)資料
| 型號： | MAX181 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | Completed ,8 Channel 12 Bits Data Acquisition System(100ksps,8通道，并行，12位A/D轉(zhuǎn)換器) |
| 中文描述： | 完備的100ksps、8通道、12位數(shù)據(jù)采集系統(tǒng) |
| 文件頁數(shù)： | 6/16頁 |
| 文件大?。?/td> | 154K |
| 代理商： | MAX181 |
M
Complete, 8-Channel,
12-Bit Data-Ac quisition S ystems
6
_______________________________________________________________________________________
CHARACTERISTICS
SYMBOL
CONDITIONS (Notes 3, 9)
DEVICE
TYPES
GROUP A
SUB-
GROUPS
LIMITS
MIN
MAX
UNITS
All
9
110
ns
–—to –————Fall Delay
t
20
10, 11
150
All
9
125
ns
–———to Data Out Valid
t
21
C
L
= 100pF (Note 10)
10, 11
170
–—, –—–or –W—–to CLK
Setup Time for 15 Clock
Conversion
–—, –—–or –W—–to CLK
Setup Time for 16 Clock
Conversion
t
22
(Note 5)
All
220
ns
t
23
(Note 5)
All
0
ns
HBEN to –—–or –W—–
Hold Time
t
19
All
9, 10, 11
0
ns
C
L
= 50pF
TABLE 2. TIMING CHARACTERISTICS (continued)
Note 1:
V
DD
= +5V ±5%, V
SS
= -12V ±5% or -15V ±5%, REFIN = -5V, internal reference mode, bipolar mode, slow-memory mode
(see text), f
CLK
= 1.6MHZ external, MAX180/MAX181 all grades, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Performance at power-supply tolerance limits guaranteed by power-supply rejection test.
V
DD
= +5V, V
SS
= -12V, f
CLK
= 1.6MHz, internal reference mode, T
A
= T
MIN
to T
MAX
, unless otherwise noted.
Typical change over temperature is ±1LSB.
Characteristics supplied for use as a typical design limit, but not production tested.
FS Tempco =
FS/
T, where FS is full-scale change from T
A
= +25°C to T
MIN
or to T
MAX
.
REFIN TC =
REFIN/
T, where
REFIN is reference voltage change from T
A
= +25°C to T
MIN
or to T
MAX
.
Load current should remain constant during conversion. This current is in addition to the DAC input current.
All inputs are 0V to +5V swing with t
r
= t
f
= 5ns (10% to 90% of 5V) and timed from a +1.6V voltage level.
Note 10:
t
16
and t
21
are measured with the load circuits of Figure 1 (C
L
= 100pF) and defined as the time required for an output to
cross 0.8V or 2.4V.
Note 11:
t
17
is defined as the time required for the data lines to change 0.5V when the circuit load is as shown in Figure 2 (C
L
= 10pF).
Note 2:
Note 3:
Note 4:
Note 5:
Note 6:
Note 7:
Note 8:
Note 9:
DGND
3k
C
L
DN
+5V
3k
C
L
b. V
OL
to High-Z
a. V
OH
to High-Z
DN
DGND
Figure 1. Load Circuits for Bus-Relinquish Time
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