參數(shù)資料
型號: MAX1800
廠商: Maxim Integrated Products, Inc.
英文描述: Digital Camera Step-Up Power Supply
中文描述: 數(shù)碼相機(jī)升壓型電源
文件頁數(shù): 16/24頁
文件大?。?/td> 461K
代理商: MAX1800
M
Digital Camera Step-Up
Power Supply
16
______________________________________________________________________________________
To determine the compensation components:
1) Find the frequency of the right-half-plane zero:
where V
POUT
is the output voltage, I
LOAD(MAX)
is the
maximum load current, L is the inductor value, and
D
M
is the duty-cycle under maximum load,
specifically:
[
+
(
where I
LIM
is the average inductor current under
maximum load, ESR
L
is the equivalent series resis-
tance of the inductor, R
PCH
and R
NCH
are the on-
state drain-source resistance of the P-channel switch
(200m
typ) and N-channel switch (100m
typ),
respectively.
2) Specify the control-loop crossover frequency (the
frequency at which the loop gain drops to unity) at
one-fifth the frequency of the right-half-plane zero:
f
CROSS
= f
RHPZ
/ 5
3) Find the DC open-loop voltage gain:
where V
REF
is the 1.25V reference voltage, A
VCOMP
is the DC voltage gain of the internal error amplifier
(2000), A
VCS
is the transresistance gain of the
internal current-sense amplifier (0.375), and D
M
is
the maximum duty cycle determined in step 1 above.
With these parameter values, the open-loop voltage
gain is:
4) Set the dominant pole so that the loop crossover
occurs at the frequency specified in step 2 above:
where G
M
is the transconductance of the error ampli-
fier (typically 100μS), and C
C
is the compensation
capacitor. Subject to this condition, the compensa-
tion capacitor is:
5) Determine the pole due to the output capacitor
(f
OUT
), and set the compensation zero (f
COMPZ
) at
the same frequency. The pole occurs at:
I
OUT
OUT
2
π
where C
OUT
is the total output capacitance at POUT,
and the zero occurs at:
Thus, setting f
OUT
to f
COMZ
:
The compensation resistor R
C
(positioned in series
with the compensation capacitor) is:
6) Find the frequency of the zero (f
ESRZ
) due to the out-
put capacitance equivalent series resistance (ESR),
and set the POUT-to-OUT RC filter pole (f
FILTER
) at
the same frequency. The zero occurs at:
and the pole occurs at:
where R
F
and C
F
are the filter resistor and capacitor,
respectively. Thus:
C
OUT
ESR = R
F
C
F
To ensure that noise is reduced at OUT, choose CF
1μF. Then determine RF:
C
C
R
ESR
F
OUT
F
=
f
R C
FILTER
F
=
1
2
π
f
C
ESR
ESRZ
OUT
=
1
2
π
R
C
V
C
C
OUT
C LOAD MAX
POUT
(
=
)
I
C
R C
LOAD MAX
OUT POUT
C
(
)
=
1
f
R C
2
π
COMPZ
=
1
f
C
V
LOAD MAX
POUT
=
(
)
C
x
A
f
C
VLOOP
CROSS
=
50
10
2
π
9
f
f
A
G
A
C
DOM
CROSS
VLOOP
M
VCOMP
C
=
=
(
)
2
π
A
D
I
VLOOP
M
LOAD
=
6666 (
)
A
V
D
A
)
A
VLOOP
REF
M
VCOMP
VCS LOAD
=
(
1
D
V
V
I
R
(
ESR
V
I
R
R
M
POUT
IN
LIM
PCH
+
L
POUT
LIM
PCH
NCH
=
+
+
)
]
)
f
V
2
D
I
L
RHPZ
POUT
π
M
LOAD MAX
=
(
1
)
(
)
2
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