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參數(shù)資料
| 型號： | MAX1741EUB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC TRANSLATOR LEVEL 10-UMAX |
| 產品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 2,500 |
| 應用： | 智能卡 |
| 接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 電源電壓： | 1.43 V ~ 5.5 V，2.25 V ~ 5.5 V |
| 封裝/外殼： | 10-TFSOP，10-MSOP（0.118"，3.00mm 寬） |
| 供應商設備封裝： | 10-µMAX |
| 包裝： | 帶卷 (TR) |
| 安裝類型： | 表面貼裝 |
MAX1740/MAX1741
SIM/Smart Card Level Translators
in MAX
_______________________________________________________________________________________
7
NAME
2
DVCC
3
CIN
4
RIN
—
5
DDRV
8
CLK
7
RST
6
GND
5
—
SHDN
10
IO
9
VCC
Pin Description
Card-Side Bidirectional Input/Output. An open-drain output with a 10k
pull-up resistor to
VCC. For bidirectional data transfer, connect to an open-drain card output capable of sink-
ing 1mA while pulling IO low. Actively pulled low during shutdown.
Supply Voltage for Card-Side Digital Pins. Set at +2.25V to +5.5V. Proper supply bypass-
ing is required to meet ±10kV ESD specifications.
Clock Output to Card. Actively pulled low during shutdown.
Reset Output to Card. Actively pulled low during shutdown.
System Controller and Card Ground
Shutdown Mode Input. Driving SHDN low reduces the total supply current to less than
2A. In shutdown mode, RST, CLK, and IO are actively pulled low and the transfer gate
between DATA and IO is disabled. When not used, connect SHDN to DVCC.
Optional System Controller Data Input. Connect to controllers without an open-drain out-
put. When not used, connect DDRV to DVCC.
System Controller Reset Input
System Controller Clock Input
Supply Voltage for System Controller Digital Pins. Set at +1.425V to +5.5V.
FUNCTION
1
DATA
1
System Controller Data Input/Output. An open-drain input/output with a 20k
pull-up
resistor to DVCC. For bidirectional data transfer, connect to an open-drain controller output
capable of sinking 1mA while pulling DATA low. If the controller is not open drain, use
DDRV to send data and DATA to receive data.
MAX1740
MAX1741
PIN
Detailed Description
The MAX1740/MAX1741 provide the necessary level
translation for interfacing with subscriber identity mod-
ules (SIMs) and smart cards in multivoltage systems.
These devices operate with logic supply voltages
between +1.425V and +5.5V on the controller side
(DVCC) and between +2.25V and +5.5V on the card side
(VCC). The total supply current (IDVCC + IVCC) is 2.5A
(max) while operating in an idle state (see Electrical
Characteristics). Figure 2 shows a typical application cir-
cuit and functional diagram.
Level Translation
The MAX1740/MAX1741 provide level translators for a
clock input, a reset input, and a bidirectional data
input/output. The clock and reset inputs (CIN and RIN)
are level shifted from the controller-side supply rails
(DVCC to GND) to the card-side supply rails (VCC to
GND). When connected to an open-drain controller out-
put, DATA and IO provide bidirectional level translation.
GND
IO
CLK
RST
VCC
DVCC
+1.8V
+3.0V OR
+5.0V
30pF
MAX1740
MAX1741
SHDN*
RIN
CIN
DDRV*
DATA
SHDN FOR MAX1740 ONLY
DDRV FOR MAX1741 ONLY
*
NOTE: ALL CAPACITANCES INCLUDE CAPACITIVE LOADS OF
TEST PROBES AND BOARD LAYOUT.
Figure 1. MAX1740/MAX1741 Test Circuit
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