參數(shù)資料
型號(hào): MAX1710
廠商: Maxim Integrated Products, Inc.
英文描述: High-Speed, Digitally Adjusted Step-Down Controllers for Notebook CPUs
中文描述: 高速、數(shù)字可調(diào)、降壓型控制器,用于筆記本電腦
文件頁(yè)數(shù): 20/28頁(yè)
文件大?。?/td> 299K
代理商: MAX1710
M
High-S peed, Digitally Adjusted
S tep-Down Controllers for Notebook CPUs
20
______________________________________________________________________________________
where C
RSS
is the reverse transfer capacitance of Q1
and I
GATE
is the peak gate-drive source/sink current (1A
typical).
For the low-side MOSFET, Q2, the worst-case power dis-
sipation always occurs at maximum battery voltage:
PD(Q2) = (1 - V
OUT
/ V
BATT(MAX)
)
·
I
LOAD2
·
R
DS(ON)
The absolute worst case for MOSFET power dissipation
occurs under heavy overloads that are greater than
I
LOAD(MAX)
but are not quite high enough to exceed the
current limit and cause the fault latch to trip. To protect
against this possibility, you must “overdesign” the circuit
to tolerate I
LOAD
= I
LIMIT(HIGH)
+ (LIR / 2)
·
I
LOAD(MAX)
,
where I
LIMIT(HIGH)
is the maximum valley current allowed
by the current-limit circuit, including threshold tolerance
and on-resistance variation. This means that the
MOSFETs must be very well heatsinked. If short-circuit
protection without overload protection is enough, a nor-
mal I
LOAD
value can be used for calculating component
stresses.
Choose a Schottky diode D1 having a forward voltage
low enough to prevent the Q2 MOSFET body diode from
turning on during the dead time. As a general rule, a
diode having a DC current rating equal to 1/3 of the load
current is sufficient. This diode is optional, and if efficien-
cy isn’t critical it can be removed.
Application Issues
Dropout Performance
The output voltage adjust range for continuous-conduc-
tion operation is restricted by the non-adjustable 500ns
(max) minimum off-time one-shot. For best dropout per-
formance, use the slowest (200kHz) on-time setting.
When working with low input voltages, the duty-factor
limit must be calculated using worst-case values for on
and off-times. Manufacturing tolerances and internal
(
)
(
)
PD switching
C
V
f I
I
RSS
BATT MAX
LOAD
GATE
=
2
V+
SHDN
SKIP
V
CC
V
IN
= 7V TO24V*
REF
DAC
INPUTS
ON/OFF
CC
0.22
μ
F
470pF
DL
D0
D1
D2
D3
D4
LX
BST
5
DH
PGND
GND
FB
Q1
+5V
20
0.1
μ
F
1
μ
F
Q2
0.5
μ
H
0.1
μ
F
1nF
C1
1k
R1
C2
CPU
1.6V AT 7A
1k
1k
V
DD
FBS
GNDS
MAX1711
R2
C1 = 4 x 4.7
μ
F/25V TAIYOYUDEN (TMK325BJ475K)
C2 = 6 x 47
μ
F/10V TAIYOYUDEN (LMK550BJ476KM)
R1 + R2 = 5m
MINIMUM OF PCB TRACE RESISTANCE (TOTAL)
TON
* FOR HIGHER MINIMUM INPUT VOLTAGE,
*
LESS OUTPUT CAPACITANCE IS REQUIRED.
Figure 7. All-Ceramic-Capacitor Application
TON
SETTING
(kHz)
APPROXIMATE
K-FACTOR
ERROR (%)
MIN V
BATT
AT V
OUT
= 2V
(V)
200
±10
2.6
300
±10
2.9
400
±12.5
3.2
550
±12.5
3.6
K
FACTOR
(μs-V)
5
3.3
2.5
1.8
Table 5. Approximate K-Factors Errors
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