M
High-S peed S tep-Down Controllers with
S ync hronous Rec tific ation for CPU Power
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15
error signal. Since average inductor current is nearly
the same as peak current (assuming the inductor value
is set relatively high to minimize ripple current), the cir-
cuit acts as a switch-mode transconductance amplifier.
It pushes the second output LC filter pole, normally
found in a duty-factor-controlled (voltage-mode) PWM,
to a higher frequency. To preserve inner-loop stability
and eliminate regenerative inductor current staircasing,
a slope-compensation ramp is summed into the main
PWM comparator. As the high-side switch turns off, the
synchronous rectifier latch is set. The low-side switch
turns on 30ns later and stays on until the beginning of
the next clock cycle. Under fault conditions where the
inductor current exceeds the maximum current-limit
threshold, the high-side latch resets, and the high-side
switch turns off.
Internal Referenc e
The internal 3.5V reference (REF) is accurate to ±1%
from 0°C to +85°C, making REF useful as a system ref-
erence. Bypass REF to AGND with a 0.1μF (min)
ceramic capacitor. A larger value (such as 1μF) is rec-
ommended for high-current applications. Load regula-
tion is 10mV for loads up to 100μA. Loading REF
reduces the main output voltage slightly, according to
the reference-voltage load-regulation error (see Typical
Operating Characteristics). Reference undervoltage
lockout is between 2.7V and 3V. Short-circuit current is
less than 4mA.
S ync hronous-Rec tifier Driver
Synchronous rectification reduces conduction losses in
the rectifier by shunting the normal Schottky diode or
MOSFET body diode with a low-on-resistance MOSFET
switch. The synchronous rectifier also ensures proper
start-up by precharging the boost-charge pump used
for the high-side switch gate-drive circuit. Thus, if you
must omit the synchronous power MOSFET for cost or
other reasons, replace it with a small-signal MOSFET,
such as a 2N7002.
The DL drive waveform is simply the complement of the
DH high-side drive waveform (with typical controlled
dead time of 30ns to prevent cross-conduction or
shoot-through). The DL output’s on-resistance is 0.7
(typ) and 2
(max).
BS T High-S ide Gate-Driver S upply
and MOS FET Drivers
Gate-drive voltage for the high-side N-channel switch is
generated using a flying-capacitor boost circuit (Fig-
ure 5). The capacitor is alternately charged from the
+5V supply and placed in parallel with the high-side
MOSFET’s gate and source terminals.
On start-up, the synchronous rectifier (low-side
MOSFET) forces LX to 0V and precharges the BST
capacitor (C4) to 5V through a diode (D2). This pro-
vides the necessary enhancement voltage to turn on
the high-side switch. On the next half-cycle, the PWM
control logic turns on the high-side MOSFET by closing
an internal switch between BST and DH. As the MOS-
FET turns on, the LX node rises to the input voltage, an
action that boosts the 5V gate-drive signal above the
+5V supply. DH on-resistance is 0.7
(typical) and 2
(max). Do not bias D2 with voltages greater than 5.5V,
as this will destroy the DH gate driver.
A 0.1μF minimum ceramic capacitor is recommended for
the boost supply. Use a low-power, SOT23 Schottky
diode to minimize reduction of the gate drive from the
diode’s forward voltage. Use a low-leakage Schottky
diode, such as a CMPSH-3 from Central Semiconductor
or a 1N4148, to prevent reverse leakage from discharg-
ing the BST capacitor when the ambient temperature is
high. Place the BST capacitor and diode within 0.4 in.
(10mm) of the BST pin.
Gate-drive resistors (R9 and R10) can often be useful
to reduce jitter in the switching waveforms by slowing
down the fast-slewing LX node and reducing ground
bounce at the controller IC. Low-valued resistors from
around 1
to 5
are sufficient for many applications.
C4
D2
V
IN
= 5V
V
DD
N1
R10
DH
LEVEL
TRANSLATOR
CONTROL AND
DRIVE LOGIC
N2
R9
PGND
R9 AND R10
ARE OPTIONAL
LX
DL
BST
MAX1624
MAX1625
Figure 5. Boost Supply for Gate Drivers