參數(shù)資料
型號: MAX1621EEE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 穩(wěn)壓器
英文描述: Digitally Adjustable LCD Bias Supplies
中文描述: SWITCHING CONTROLLER, 200 kHz SWITCHING FREQ-MAX, PDSO16
封裝: 0.150 INCH, 0.025 INCH PITCH, QSOP-16
文件頁數(shù): 5/20頁
文件大?。?/td> 253K
代理商: MAX1621EEE
M
Digitally Adjustable LCD Bias S upplies
_______________________________________________________________________________________
5
TIMING CHARACTERISTICS
(V
DD
= 3.3V, V
BATT
= 10V,
T
A
= -40°C to +85°C
. Typical values are at T
A
= +25°C, unless otherwise noted. Limits over this
temperature range are guaranteed by design.)
CONDITIONS
SYMBOL
PARAMETER
MAX1620
(Figure 1)
4
Stop Condition SCL_ to SDA_
Setup Time
μs
t
SU:STO
μs
4
t
HD:STA
Start Condition SDA_ to SCL_
Hold Time
μs
4.7
t
SU:STA
Start Condition SCL_ to SDA_
Setup Time
μs
4
t
HIGH
SCL High Time
μs
4.7
t
LOW
SCL Low Time
ns
300
t
F
SCL/SDA Fall Time
μs
μs
μs
μs
1
1
1
1
t
1
t
2
t
3
t
4
Pulse Width High (UP, DN)
Pulse Width Low (UP, DN)
Pulse Separation (UP, DN)
Counter Reset Time
MAX1621
(Figures 2 and 3)
μs
1
t
R
SCL/SDA Rise Time
ns
0
t
HD:DAT
SCL_ to SDA_ Data-Hold Time
ns
500
t
SU
:
DAT
SDA_ to SCL_ Data-Setup Time
UNITS
MIN
TYP
MAX
Note 1:
The setting in the DAC is guaranteed to remain valid as long as V
DD
is greater than the UVLO threshold.
Note 2:
BATT Operating Range is guaranteed by the Microsecond-Volt Time Constant specification.
Note 3:
Current sourced from a pin is denoted as positive current. Current sunk into a pin is denoted as negative current.
Note 4:
Guaranteed by design.
__________________________________________Typic al Operating Charac teristic s
(V
DD
= 5V, V
BATT
= 10V, L1 = 100μH, T
A
= +25°C, unless otherwise noted.)
0.70
0.75
0.80
0.85
0.90
0.95
1.00
0
10
20
OUTPUT CURRENT (mA)
30
40
50
60
70
EFFICIENCY vs. OUTPUT CURRENT
M
E
+25V
+15V
0.70
0.75
0.80
0.85
0.90
0.95
1.00
0
10
20
OUTPUT CURRENT (mA)
30
40
50
60
70
EFFICIENCY vs. OUTPUT CURRENT
M
E
-25V
-15V
0.70
0.75
0.80
0.85
0.90
0.95
1.00
12
14
16
18
20
22
24
26
EFFICIENCY vs. OUTPUT VOLTAGE
M
OUTPUT VOLTAGE (V)
E
+10mA
+20mA
1
SCL Falling Time to SDA Valid
Master Clocking in Data
μs
t
DV
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