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參數(shù)資料
| 型號(hào)： | MAX1604EAI |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 電源管理 |
| 英文描述： | Dual-Channel CardBus and PCMCIA Power Switches with SMBus⑩ Serial Interface |
| 中文描述： | 2-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO28 |
| 封裝： | 0.200 INCH, SSOP-28 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 190K |
| 代理商： | MAX1604EAI |
M
Dual-Channel CardBus and PCMCIA
Power S witc hes with S MBus S erial Interfac e
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VL = VY = 3.3V, VX = 5V, 12INA = 12INB = 12V, T
A
= 0°C to +85°C, unless otherwise noted. Typical values are at T
A
= +25°C.)
PARAMETER
SMB Input Capacitance
SMBCLK Clock Frequency
SMBus spec = 10kHz min
t
LOW
10% to 10% points
MIN
TYP
5
MAX
UNITS
pF
kHz
SMBCLK Clock High Time
4
μs
t
HIGH
90% to 90% points
SMBCLK Clock Low Time
4.7
μs
DC
100
SMBSUS
, SMBCLK, SMBDATA
CONDITIONS
Logic Input Bias Current
-1
1
μA
ADR,
SMBSUS
, SMBCLK, SMBDATA
SMB Start-Condition Hold Time
SMB Stop-Condition Setup Time
4
4
μs
μs
ADR Input High Voltage
1.5
V
Bus Free Time
ADR Input Low Voltage
4.7
μs
V
0.6
t
BUF
between start and stop conditions
SMB Data Valid to SMBCLK Rising-
Edge Time
500
ns
SMB Data Hold Time
0
t
HD:STA
10% of SMBDATA to 90% of SMBCLK
t
SU:STO
90% of SMBCLK to 10% of SMBDATA
t
SU:DAT
10% or 90% of SMBDATA to
10% of SMBCLK
ns
SMB Repeated Start-Condition
Setup Time
250
ns
t
HD:DAT
(Note 5)
t
SU:STA
90% to 90% points
Start-Condition Setup
SCL Fall to SDA Valid
(Master Clocking-In Data)
100
1000
ns
4.7
μs
Note 3:
Not production tested.
Note 4:
Thermal limit not active in standby state (all switches programmed to GND or high-Z state).
Note 5:
A transition must internally provide at least a hold time in order to bridge the undefined region (300ns max) of the falling
edge of SMBCLK.
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