參數(shù)資料
型號(hào): MAX16048
廠商: Maxim Integrated Products, Inc.
英文描述: 12-Channel/8-Channel EEPROM-Programmable System Managers with Nonvolatile Fault Registers
中文描述: 12/8通道EEPROM可編程系統(tǒng)管理器,提供非易失故障寄存器
文件頁(yè)數(shù): 6/68頁(yè)
文件大?。?/td> 570K
代理商: MAX16048
M
12-Channel/8-Channel EEPROM-Programmable
System Managers with Nonvolatile Fault Registers
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(V
CC
= 3V to 14V, T
A
= -40°C to +85°C, unless otherwise specified. Typical values are at V
CC
= 3.3V, T
A
= +25°C.) (Note 1)
PARAMETER
SYMBOL
V
CC
shorted to GND, SCL/SDA at 0V or
3.3V
Input Leakage Current
CONDITIONS
MIN
TYP
MAX
UNITS
-1
+1
-1
+1
0.4
μA
Output-Voltage Low
Input Capacitance
SMBUS TIMING
Serial Clock Frequency
Bus Free Time Between STOP
and START Condition
START Condition Setup Time
START Condition Hold Time
STOP Condition Setup Time
Clock Low Period
Clock High Period
Data Setup Time
Output Fall Time
Data Hold Time
Pulse Width of Spike Suppressed
JTAG INTERFACE
TDI, TMS, TCK Logic-Low Input
Voltage
TDI, TMS, TCK Logic-High Input
Voltage
TDO Logic-Output Low Voltage
TDO Logic-Output High Voltage
TDO Leakage Current
TDI, TMS Pullup Resistors
Input/Output Capacitance
JTAG TIMING
TCK Clock Period
TCK High/Low Time
TCK to TMS, TDI Setup Time
TCK to TMS, TDI Hold Time
TCK to TDO Delay
TCK to TDO High-Impedance
Delay
EEPROM TIMING
EEPROM Byte Write Cycle Time
Note 1:
Specifications are guaranteed for the stated global conditions, unless otherwise noted. 100% production tested at T
A
= +25°C
and T
A
= +85°C. Specifications at T
A
= -40°C are guaranteed by design.
Note 2:
V
UVLO
is the minimum voltage on V
CC
to ensure the device is EEPROM configured.
Note 3:
Applies to
RESET
, fault, delay, and watchdog timeouts.
Note 4:
Total unadjusted error is a combination of gain, offset, and quantization error.
Note 5:
Guaranteed by design.
Note 6:
An additional cycle is required when writing to configuration memory for the first time.
V
OL
C
IN
I
SINK
= 3mA
V
pF
5
f
SCL
400
kHz
t
BUF
1.3
μs
t
SU:STA
t
HD:STA
t
SU:STO
t
LOW
t
HIGH
t
SU:DAT
t
OF
t
HD:DAT
t
SP
0.6
0.6
0.6
1.3
0.6
100
μs
μs
μs
μs
μs
ns
ns
μs
ns
10pF
C
BUS
400pF
From 50% SCL falling to SDA change
250
0.9
0.3
30
V
IL
Input voltage falling
0.55
V
V
IH
Input voltage rising
2
V
V
OL_TDO
V
OH_TDO
V
DBP
2.5V, I
SINK
= 2mA
V
DBP
2.5V, I
SOURCE
= 200mA
TDO high impedance
Pullup to V
DBP
0.4
V
V
μA
k
Ω
pF
2.4
-1
7
+1
13
R
JPU
C
I/O
10
5
t
1
1000
ns
ns
ns
ns
ns
t
2,
t
3
t
4
t
5
t
6
50
15
15
500
500
t
7
500
ns
t
WR
(Note 6)
10.5
12
ms
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