參數(shù)資料
型號: MAX16005DUE+
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: 電源管理
英文描述: 6-CHANNEL POWER SUPPLY MANAGEMENT CKT, PDSO16
封裝: 5 X 4.40 MM, ROHS COMPLIANT, TSSOP-16
文件頁數(shù): 21/26頁
文件大?。?/td> 280K
代理商: MAX16005DUE+
MAX16000–MAX16007
Low-Voltage, Quad-/Hex-/Octal-Voltage
P Supervisors
4
_______________________________________________________________________________________
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
REFERENCE OUTPUT (MAX16005 Only)
Reference Short-Circuit Current
Shorted to GND
0.8
mA
Reference Output Accuracy
VREF
No load
1.200
1.235
1.270
V
Line Regulation
0.005
% / V
Reference Load Regulation
Sourcing, 0
≤ IREF ≤ 40A
10
WATCHDOG TIMER (MAX16001/MAX16002/MAX16004–MAX16007)
WDI Input-Voltage Low
VIL
0.3 x
VCC
V
WDI Input-Voltage High
VIH
0.7 x
VCC
V
WDI Pulse Width
(Note 5)
50
ns
Watchdog Timeout Period
tWDI
1.12
1.6
2.40
s
Watchdog Startup Period
MAX16001/2/4/6/7
35
54
72
s
Watchdog Input Current
VWDI = 0 to VCC (Note 5)
-1
+1
A
VCC = 3.3V, ISINK = 2mA
0.30
WDO Output-Voltage Low
(MAX16005 Only)
VOL
VCC = 2.5V, ISINK = 1.2mA
0.30
V
WDO Output-Voltage High
(MAX16005 Only)
VOH
VCC
≥ 2.0V, ISOURCE = 6A, WDO
deasserted
0.8 x
VCC
V
DIGITAL LOGIC
TOL Input-Voltage Low
VIL
0.3 x
VCC
V
TOL Input-Voltage High
VIH
0.7 x
VCC
V
TOL Input Current
TOL = VCC
100
nA
MARGIN Input-Voltage Low
VIL
0.3 x
VCC
V
MARGIN Input-Voltage High
VIH
0.7 x
VCC
V
MARGIN Pullup Resistance
Pulled up to VCC
12
20
28
k
MARGIN Delay Time
tMD
Rising or falling (Note 6)
50
s
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 2.0V to 5.5V, TA = -40°C to +125°C, unless otherwise specified. Typical values are at VCC = 3.3V, TA = +25°C). (Note 1)
Note 1: Devices are tested at TA = +25°C and guaranteed by design for TA = TMIN to TMAX.
Note 2: The outputs are guaranteed to be in the correct logic state down to VCC = 1V.
Note 3: Measured with WDI, MARGIN, and MR unconnected.
Note 4: The minimum and maximum specifications for this parameter are guaranteed by using the worst case of the SRT ramp cur-
rent and SRT threshold specifications.
Note 5: Guaranteed by design and not production tested.
Note 6: Amount of time required for logic to lock/unlock outputs from margin testing.
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