參數(shù)資料
型號: MAX152EWP
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: +3V, 8-Bit ADC with 1レA Power-Down
中文描述: 1-CH 8-BIT FLASH METHOD ADC, PARALLEL ACCESS, PDSO20
封裝: PLASTIC, SOP-20
文件頁數(shù): 8/12頁
文件大?。?/td> 122K
代理商: MAX152EWP
M
A minimum acquisition time (tP) is required from
INT
going low to the start of another conversion (
WR
going
low).
Options for reading data from the converter include the
following:
Using Internal Delay
The μP waits for the
INT
output to go low before read-
ing the data (Figure 4).
INT
goes low after the rising
edge of
WR
, indicating that the conversion is complete
and the result is available in the output latch. With
CS
low, data outputs D0-D7 can be accessed by pulling
RD
low.
INT
is then reset by the rising edge of
CS
or
RD
.
Fastest Conversion: Reading Before Delay
An external method of controlling the conversion time is
shown in Figure 5. The internally generated delay
tINTL varies slightly with temperature and supply volt-
age, and can be overridden with
RD
to achieve the
fastest conversion time.
RD
is brought low after the ris-
ing edge of
WR
, but before
INT
goes low. This com-
pletes the conversion and enables the output buffers
(D0-D7) that contain the conversion result.
INT
also
goes low after the falling edge of
RD
and is reset on the
rising edge of
RD
or
CS
. The total conversion time is
therefore: tCWR= tWR(600ns) + tRD(800ns) + tACC1
(400ns) = 1800ns.
S tand-Alone Operation
Besides the two standard WR-RD mode options, stand-
alone operation can be achieved by connecting
CS
and
RD
low (Figure 6). A conversion is initiated by
pulling
WR
low. Output data can be read by either
edge of the next
WR
pulse.
+3V, 8-Bit ADC with 1μA Power-Down
8
_______________________________________________________________________________________
tP
tINTL
WR
INT
NEW DATA
tWR
tIHWR
tID
OLD DATA
D0-D7
Figure 6. Stand-Alone Mode Timing (
CS
=
RD
= 0) (MODE = 1)
VREF-
MAX152
VDD
VREF+
0.1μF
VIN
VIN+
VIN-
GND
+3V
1
10
20
12
11
4.7μF
Figure 7a. Power Supply as Reference
+3V
0.1
μF
4
VREF-
MAX152
VREF+
VIN
8
1
3
7
0.1
μF
4.7
μF
2
6
GND
VDD
10
1
20
12
11
+2.5V
3
LM10
VIN+
Figure 7b. External Reference, +2.5V Full Scale
+3V
0.1μF
12
VREF-
MAX152
VREF+
VIN
10
1
20
11
0.1μF
4.7μF
GND
VDD
0.1μF
VIN-
1.2V
VIN+
*CURRENT PATH MUST STILL
EXIST FROM VIN- TOGND.
Figure 7c. Input Not Referenced to GND
+3V
PWRDN
C1
2.2μF
MTD3055EL
N
MAX152
VREF-
VDD
VREF+
PWRDN
MAX872
+
Figure 7d. An N-channel MOSFET switches off the reference
load during power-down.
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