參數(shù)資料
型號(hào): MAX1517
廠商: Maxim Integrated Products, Inc.
元件分類: DC/DC變換器
英文描述: TFT-LCD DC-DC Converters with Operational Amplifiers
中文描述: TFT-LCD DC-DC轉(zhuǎn)換器,帶有運(yùn)算放大器
文件頁(yè)數(shù): 20/26頁(yè)
文件大?。?/td> 919K
代理商: MAX1517
M
TFT-LCD DC-DC Converters with
Operational Amplifiers
20
______________________________________________________________________________________
Output-Capacitor Selection
The total output voltage ripple has two components: the
capacitive ripple caused by the charging and discharg-
ing of the output capacitance, and the ohmic ripple due
to the capacitor’s equivalent series resistance (ESR).
where I
PEAK
is the peak inductor current (see the
Inductor Selection
section). For ceramic capacitors, the
output voltage ripple is typically dominated by
V
RIPPLE(C)
. The voltage rating and temperature charac-
teristics of the output capacitor must also be considered.
Input-Capacitor Selection
The input capacitor (C
IN
) reduces the current peaks
drawn from the input supply and reduces noise injec-
tion into the IC. A 22μF ceramic capacitor is used in the
Typical Applications Circuit
(Figure 1) because of the
high source impedance seen in typical lab setups.
Actual applications usually have much lower source
impedance since the step-up regulator often runs
directly from the output of another regulated supply.
Typically, C
IN
can be reduced below the values used in
the
Typical Applications Circuit
. Ensure a low-noise
supply at IN by using adequate C
IN
. Alternately,
greater voltage variation can be tolerated on C
IN
if IN is
decoupled from C
IN
using an RC lowpass filter (see
R10 and C18 in Figure 1).
Rectifier Diode
The MAX1516/MAX1517/MAX1518s’ high switching fre-
quency demands a high-speed rectifier. Schottky
diodes are recommended for most applications
because of their fast recovery time and low forward
voltage. In general, a 2A Schottky diode complements
the internal MOSFET well.
Output-Voltage Selection
The output voltage of the main step-up regulator can be
adjusted by connecting a resistive voltage-divider from
the output (V
MAIN
) to AGND with the center tap connect-
ed to FB (see Figure 1). Select R2 in the 10k
to 50k
range. Calculate R1 with the following equation:
where V
FB
, the step-up regulator’s feedback set point,
is 1.236V. Place R1 and R2 close to the IC.
Generating Output Voltages >13V
The maximum output voltage of the step-up regulator is
13V, which is limited by the absolute maximum rating of
the internal power MOSFET. To achieve higher output
voltages, an external n-channel MOSFET can be cascod-
ed with the internal FET (Figure 8). Since the gate of the
external FET is biased from the input supply, use a logic-
level FET to ensure that the FET is fully enhanced at the
minimum input voltage. The current rating of the FET
needs to be higher than the IC’s internal current limit.
Loop Compensation
Choose R
COMP
to set the high-frequency integrator
gain for fast transient response. Choose C
COMP
to set
the integrator zero to maintain loop stability.
For low-ESR output capacitors, use the following equa-
tions to obtain stable performance and good transient
response:
To further optimize transient response, vary R
COMP
in
20% steps and C
COMP
in 50% steps while observing
transient-response waveforms.
Charge Pumps
Selecting the Number of Charge-Pump Stages
For highest efficiency, always choose the lowest num-
ber of charge-pump stages that meet the output
requirement. Figures 9 and 10 show the positive and
negative charge-pump output voltages for a given
V
MAIN
for one-, two-, and three-stage charge pumps.
The number of positive charge-pump stages is given by:
where n
POS
is the number of positive charge-pump
stages, V
GON
is the gate-on linear-regulator REG P out-
put, V
MAIN
is the main step-up regulator output, V
D
is
the forward-voltage drop of the charge-pump diode,
and V
DROPOUT
is the dropout margin for the linear reg-
ulator. Use V
DROPOUT
= 0.3V.
n
V
V
V
V
V
POS
GON
DROPOUT
MAIN
×
MAIN
D
=
+
2
R
V
L I
V
OUT
MAIN MAX
V
C
C
C
I
R
COMP
IN
OUT
(
OUT
MAIN MAX
×
COMP
OUT
×
)
COMP
×
×
×
×
315
10
)
(
R
R
V
V
MAIN
FB
1
2
1
=
×
V
V
V
V
I
C
V
V
V
and
V
I
RIPPLE
RIPPLE( )
RIPPLE ESR
RIPPLE( )
MAIN
OUT
MAIN
MAIN OSC
IN
RIPPLE ESR
PEAK ESR COUT
=
+
(
)
(
)
(
)
,
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