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參數(shù)資料
| 型號(hào)： | MAX148BEPP+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 21/23頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SERIAL 20-DIP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 18 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 133k |
| 數(shù)據(jù)接口： | MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 889mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 通孔 |
| 封裝/外殼： | 20-DIP（0.300"，7.62mm） |
| 供應(yīng)商設(shè)備封裝： | 20-PDIP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極 |
+2.7V to +5.25V, Low-Power, 8-Channel,
Serial 10-Bit ADCs
MAX148/MAX149
7
Pin Description
Figure 1. Load Circuits for Enable Time
Figure 2. Load Circuits for Disable Time
PIN
NAME
FUNCTION
1–8
CH0–CH7
Sampling Analog Inputs
9
COM
Ground Reference for Analog Inputs. COM sets zero-code voltage in single-ended mode. Must be
stable to ±0.5 LSB.
10
SHDN
Three-Level Shutdown Input. Pulling SHDN low shuts the MAX148/MAX149 down; otherwise, they
are fully operational. Pulling SHDN high puts the reference-buffer amplifier in internal compensation
mode. Leaving SHDN unconnected puts the reference-buffer amplifier in external compensation
mode.
11
VREF
Reference-Buffer Output/ADC Reference Input. Reference voltage for analog-to-digital conversion.
In internal reference mode (MAX149 only), the reference buffer provides a 2.500V nominal output,
externally adjustable at REFADJ. In external reference mode, disable the internal buffer by pulling
REFADJ to VDD.
12
REFADJ
Input to the Reference-Buffer Amplifier. To disable the reference-buffer amplifier, tie REFADJ to VDD.
13
AGND
Analog Ground
14
DGND
Digital Ground
15
DOUT
Serial-Data Output. Data is clocked out at SCLK’s falling edge. High impedance when CS is high.
16
SSTRB
Serial-Strobe Output. In internal clock mode, SSTRB goes low when the MAX148/MAX149 begin
the A/D conversion, and goes high when the conversion is finished. In external clock mode, SSTRB
pulses high for one clock period before the MSB decision. High impedance when CS is high
(external clock mode).
17
DIN
Serial-Data Input. Data is clocked in at SCLK’s rising edge.
18
CS
Active-Low Chip Select. Data will not be clocked into DIN unless CS is low. When CS is high, DOUT
is high impedance.
19
SCLK
Serial-Clock Input. Clocks data in and out of serial interface. In external clock mode, SCLK also sets
the conversion speed (duty cycle must be 40% to 60%).
20
VDD
Positive Supply Voltage
a) HIGH-Z TO VOH AND VOL TO VOH
b) HIGH-Z TO VOL AND VOH TO VOL
DOUT
DGND
6kI
VDD
DGND
DOUT
6kI
CLOAD
50pF
CLOAD
50pF
b) VOL TO HIGH-Z
a) VOH TO HIGH-Z
DOUT
DGND
6kI
CLOAD
50pF
VDD
DOUT
DGND
6kI
CLOAD
50pF
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