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參數(shù)資料
| 型號： | MAX146BMJP |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +2.7Low-Power, 8-Channel, Serial 12-Bit ADCs |
| 中文描述： | 8-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, CDIP20 |
| 封裝： | CERAMIC, DIP-20 |
| 文件頁數(shù)： | 15/24頁 |
| 文件大小： | 198K |
| 代理商： | MAX146BMJP |
M
+2.7V, Low-Power, 8-Channel,
S erial 12-Bit ADCs
______________________________________________________________________________________
15
SCLK
DIN
DOUT
CS
S
CONTROL BYTE 0
CONTROL BYTE 1
S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONVERSION RESULT 1
SSTRB
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
CONTROL BYTE 2
S
1
8
1
15
15
8
1
CS
SCLK
DIN
DOUT
S
1
8
16
1
8
16
CONTROL BYTE 0
CONTROL BYTE 1
S
CONVERSION RESULT 0
B11 B10 B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
B11 B10 B9 B8
CONVERSION RESULT 1
Figure 11a. External Clock Mode, 15 Clocks/Conversion Timing
Figure 11b. External Clock Mode, 16 Clocks/Conversion Timing
Data Framing
The falling edge of
CS
does
not
start a conversion.
The first logic high clocked into DIN is interpreted as a
start bit and defines the first bit of the control byte. A
conversion starts on SCLK’s falling edge, after the eighth
bit of the control byte (the PD0 bit) is clocked into DIN.
The start bit is defined as follows:
The first high bit clocked into DIN with
CS
low any
time the converter is idle; e.g., after V
DD
is applied.
OR
The first high bit clocked into DIN after bit 5 of a con-
version in progress is clocked onto the DOUT pin.
If CS is toggled before the current conversion is com-
plete, the next high bit clocked into DIN is recognized as
a start bit; the current conversion is terminated, and a
new one is started.
The fastest the MAX146/MAX147 can run with
CS
held
low between conversions is 15 clocks per conversion.
Figure 11a shows the serial-interface timing necessary to
perform a conversion every 15 SCLK cycles in external
clock mode. If
CS
is tied low and SCLK is continuous,
guarantee a start bit by first clocking in 16 zeros.
Most microcontrollers (μCs) require that conversions
occur in multiples of 8 SCLK clocks; 16 clocks per con-
version is typically the fastest that a μC can drive the
MAX146/MAX147. Figure 11b shows the serial-
interface timing necessary to perform a conversion every
16 SCLK cycles in external clock mode.
__________ Applic ations Information
Power-On Reset
When power is first applied, and if
SHDN
is not pulled
low, internal power-on reset circuitry activates the
MAX146/MAX147 in internal clock mode, ready to con-
vert with SSTRB = high. After the power supplies stabi-
lize, the internal reset time is 10μs, and no conversions
should be performed during this phase. SSTRB is high
on power-up and, if
CS
is low, the first logical 1 on DIN
is interpreted as a start bit. Until a conversion takes
place, DOUT shifts out zeros. (Also see Table 4.)
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