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參數(shù)資料
| 型號： | MAX1462CCM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | Low-Voltage, Low-Power, 16-Bit Smart ADC |
| 中文描述： | 1-CH 12-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 242K |
| 代理商： | MAX1462CCM |
M
Low-Voltage, Low-Power,
16-Bit Smart ADC
4
_______________________________________________________________________________________
Pin Description
End of Conversion Output. A high-to-low transition of the EOC pulse can be used to latch the Parallel
Digital Output (pins D[11...0]).
EOC
23
Parallel Digital Output - Bit 0 (LSB)
D0
24
Parallel Digital Output - Bit 1
D1
25
Parallel Digital Output - Bit 2
D2
26
Reset Input. When TEST is high, a low-to-high transition on
RESET
enables the MAX1462 to accept
commands from the test system. This input is ignored when TEST is low. Internally pulled high to V
DD
with a 1M
(typ) resistor.
RESET
22
Serial Data Output. Used only during programming/testing. SDO allows the test system to monitor the
DSP registers. The MAX1462 returns to the test system results of the DSP current instruction. SDO is
high impedance when TEST is low.
SDO
21
Serial Data Input/Output. Used only during programming/testing, when the TEST pin is high. The test
system sends commands to the MAX1462 through SDIO. The MAX1462 returns the current instruction
ROM address and data being executed by the DSP to the test system. SDIO is internally pulled to V
SS
with a 1M
(typ) resistor. SDIO goes high impedance when either CS1 or CS2 is low and remains in
this state until the test system initiates conversion.
SDIO
20
Parallel Digital Output - Bit 10
D10
10
Parallel Digital Output - Bit 11 (MSB)
D11
11
Positive Supply Voltage Input. Connect a 0.1μF bypass capacitor from V
DD
to V
SS
. Pins 14, 37, and 38
must all be connected to the positive power supply on the PC board.
V
DD
14, 37, 38
Negative Supply Input
V
SS
15
Chip-Select Input. The MAX1462 is selected when CS1 and CS2 are both high. When either CS1 or
CS2 is low, all digital outputs are high impedance and all digital inputs are ignored. CS1 and CS2 are
internally pulled high to V
DD
with a 1M
(typ) resistor.
CS1,
CS2
16, 17
Parallel Digital Output - Bit 6
D6
6
Parallel Digital Output - Bit 7
D7
7
Parallel Digital Output - Bit 8
D8
8
Parallel Digital Output - Bit 9
D9
9
Internally Connected. Leave unconnected.
I.C.
5
Optional conversion start input signal, used for extending sensor warm-up time. Internally pulled to
V
DD
with a 1M
(typ) resistor.
START
4
PIN
Analog Ground. Connect to V
DD
and V
SS
using 10k
resistors (see
Functional Diagram
).
AGND
3
No Connection. Not internally connected.
N.C.
1, 2, 12,
13, 18, 19,
31, 32, 36,
41–45
FUNCTION
NAME
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