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參數(shù)資料
| 型號(hào)： | MAX1460CCM |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | Low-Power, 16-Bit Smart ADC |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PQFP48 |
| 封裝： | TQFP-48 |
| 文件頁數(shù)： | 9/20頁 |
| 文件大?。?/td> | 204K |
| 代理商： | MAX1460CCM |
M
Low-Power, 16-Bit Smart ADC
_______________________________________________________________________________________
9
Test-System Interface: Writing Calibration
Coefficients to the DSP Registers
and EEPROM
To make the MAX1460 respond to commands from the
test system, raise the TEST pin and drive XIN with a
2MHz clock signal. It is not necessary to remove the
resonator.
RESET
must be low for at least 16 clock
cycles to initialize the MAX1460. Then, a rising transi-
tion on
RESET
begins a 32-bit serial transfer of the test-
system command word through SDIO. The test system
transitions SDIO on falling edges of the XIN clock; the
MAX1460 latches data is on the rising edge (Figure 3).
The 32-bit command word generated by the test-sys-
tem is divided into four fields (Figure 3). The 4-bit com-
mand field is interpreted in Table 4. The other fields are
usually ignored, except that command 1 hex uses the
two register fields, and command 2 hex requires an
EEPROM address. The command word fields are:
Register Data Field: Holds the calibration coeffi-
cients to be written into the MAX1460 16-bit registers
EEPROM Address Field: Holds the hexadecimal
address of the EEPROM bit to be set (from 00 hex to
7F hex)
Register Address Field: Contains the address of the
register (0 to 7) where the calibration coefficient is to
be written
Command Field: Instructs the MAX1460 to take a
particular action (Table 4)
MIN
16 CLK
CYCLES
COMMAND 1
REGISTER DATA FIELD
EEPROM ADDRESS
FIELD
REG.
ADD
COMMAND 2
COMMAND 3
COMMAND n
COMMAND
00 01 02 03 29 30 31 00 01 02 03 29 30 31 00 01 02 03 29 30 31 00 01 02 03 29 30 31
D0 D1 D2 D3 C3
NU
NU D0 D1 D2 D3 C3
NU
NU D0 D1 D2 D3 C3
NU
NU D0 D1 D2
D3
C3
NU
NU
D0 D1 D2 D3 D4 D5 D6 D7 D8 D9
D10 D11 D12 D1
3
D14
D15 E0 E1 E2 E3 E4 E5 E6 R0 R1 R2 C0 C1 C2 C3 NU NU
MSB LSB
LSB
MSB LSB
MSB LSB
MSB
NOTE: ALL TRANSITIONS MUST OCCUR WITHIN 100ns OF THE XIN CLOCK EDGE.
XIN
TEST
RESET
SDIO
Figure 3. Test-System Command Timing Diagram
TSO-0
TSO-1
TSO-2
TEMPERATURE
BRIDGE
OFFSET
Maximum
TSO
SETTING
1
1
1
7
0
1
1
6
1
0
1
5
Minimum
–
–
–
–
–
–
0
0
1
4
1
1
0
3
0
1
0
2
1
0
0
1
0
0
0
0
Table 3. Temperature Sensor Offset
(TSO) Settings
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