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參數(shù)資料
| 型號： | MAX1458AAE |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號調(diào)理 |
| 英文描述： | 1%-Accurate, Digitally Trimmed Sensor Signal Conditioner |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO16 |
| 封裝： | 5.30 MM, 0.65 MM PITCH, SSOP-16 |
| 文件頁數(shù)： | 7/20頁 |
| 文件大?。?/td> | 145K |
| 代理商： | MAX1458AAE |
a V
DD
of 5V. The output of the Offset DAC is fed into
the output summing junction where it is gained by
approximately 2.3, which increases the resulting out-
put-referred offset correction resolution to 2.8mV.
Both the Offset TC and FSOTC DACs take their refer-
ence from BDRIVE, a temperature-dependent voltage. A
nominal V
BDRIVE
of 2.5V results in a step size of 0.6mV.
The Offset TC DAC output is fed into the output sum-
ming junction where it is gained by approximately 2.3,
thereby increasing the Offset TC correction range. The
buffered FSOTC DAC output is available at FSOTC and
is connected to ISRC via R
FTC
to correct FSOTC errors.
Internal Resistors
The MAX1458 contains three internal resistors (R
ISRC
,
R
FTC
, and R
TEMP
) optimized for common silicon PRTs.
R
ISRC
(in conjunction with the FSO DAC) programs the
nominal sensor excitation current. R
FTC
(in conjunction
with the FSOTC DAC) compensates the FSOTC errors.
Both R
ISRC
and R
FTC
have a nominal value of 75k
. If
external resistors are used, R
ISRC
and R
FTC
can be dis-
abled by resetting the appropriate bit (address 07h
reset to zero) in the configuration register (Table 3).
R
TEMP
is a high-tempco resistor with a TC of
+4600ppm/°C and a nominal resistance of 100k
at
+25°C. This resistor can be used with certain sensor
types that require an external temperature sensor.
Internal EEPROM
The MAX1458 has a 128-bit internal EEPROM arranged
as eight 16-bit words. The four uppermost bits for each
register are reserved. The internal EEPROM is used to
store the following (also shown in the memory map in
Table 4):
M
1%-Ac c urate, Digitally Trimmed
S ensor S ignal Conditioner
_______________________________________________________________________________________
7
Figure 3. Bridge Excitation Circuit
V
DD
AA
≈
14I
ISRC
= I
BDRIVE
I = I
ISRC
I
SRC
FSOTC
R
ISRC
BDRIVE
V
DD
R
FTC
EXTERNAL
SENSOR
FSO
DAC
FSOTC
DAC
01h
02h
Offset Sign Bit, SOFF
PGA Gain (MSB), A2
00h
03h
04h
Offset TC Sign Bit, SOTC
PGA Gain, A1
PGA Gain (LSB), A0
DESCRIPTION
EEPROM
ADDRESS (hex)
05h
06h
Reserved “0”
Reserved “0”
07h
Internal Resistor (R
FTC
and R
ISRC
)
Selection
Input-Referred Offset (IRO) Sign Bit
09h
0Ah
Input-Referred Offset (MSB)
Input-Referred Offset
08h
0Bh
Input-Referred Offset (LSB)
Table 3. Configuration Register
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