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參數(shù)資料
| 型號： | MAX1458 |
| 廠商： | Maxim Integrated Products, Inc. |
| 英文描述： | 1%-Accurate, Digitally Trimmed Sensor Signal Conditioner |
| 中文描述： | 1%精確度、數(shù)字調(diào)節(jié)傳感器信號調(diào)理器 |
| 文件頁數(shù)： | 8/20頁 |
| 文件大?。?/td> | 145K |
| 代理商： | MAX1458 |
M
Configuration register (Table 3)
12-bit calibration coefficients for the Offset and FSO
DACs
12-bit compensation coefficients for the Offset TC
and FSOTC DACs
Two general-purpose registers available to the user
for storing process information such as serial num-
ber, batch date, and check sums
Program the EEPROM one bit at a time. The bits have
addresses from 0 to 127 (7F hex).
Configuration Register
The configuration register (Table 3) determines the
PGA gain, the polarity of the offset and offset TC coeffi-
cients, and the coarse offset correction (IRO DAC). It
also enables/disables internal resistors (R
FTC
and
R
ISRC
).
DAC Registers
The Offset, Offset TC, FSO, and FSOTC registers store
the coefficients used by their respective calibration/
compensation DACs.
1%-Ac c urate, Digitally Trimmed
S ensor S ignal Conditioner
8
_______________________________________________________________________________________
Table 4. EEPROM Memory Map
EE Address
Contents
EE Address
Contents
EE Address
Contents
EE Address
Contents
EE Address
Contents
Reserved*
EE Address
Contents
EE Address
Contents
0E
0
0C
0
0F
1
0D
0
0A
08
0B
09
06
04
07
05
02
00
Configuration
03
01
1E
0
1C
1
1F
1
1D
0
1A
18
1B
MSB
19
16
Offset
14
17
15
12
10
LSB
13
11
2E
0
2C
0
2F
1
2D
1
2A
28
2B
MSB
29
26
Offset TC
24
27
25
22
20
LSB
23
21
3E
0
3C
1
3F
1
3D
1
3A
38
3B
MSB
39
36
34
37
35
32
30
FSO
LSB
33
31
4E
1
4C
0
4F
1
4D
0
4A
48
4B
MSB
49
46
FSOTC
44
47
45
42
40
LSB
43
41
5E
0
5C
0
5F
0
5D
0
5A
0
58
0
5B
0
59
0
56
0
54
0
57
0
55
0
52
0
50
0
53
0
51
0
6E
0
6C
0
6F
0
6D
0
6A
68
6B
69
66
64
67
65
62
60
User defined bits
63
61
7E
0
7C
0
7F
0
7D
0
7A
78
7B
79
76
74
77
75
72
70
User defined bits
73
71
Note: The MAX1458 processes the Reserved Bits in the EEPROM. If these bits are not properly programmed, the configuration
and DAC registers will not be updated correctly.
* The contents of the Reserved EE Address 50–5F must all be reset to zero.
= Reserved Bits
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