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參數(shù)資料
| 型號(hào)： | MAX1457CWI |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 0.1%-Accurate Signal Conditioner for Piezoresistive Sensor Compensation |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, PDSO28 |
| 封裝： | SOP-28 |
| 文件頁數(shù)： | 10/12頁 |
| 文件大?。?/td> | 93K |
| 代理商： | MAX1457CWI |
M
7) Perform curve-fitting to test data.
8) Based on a curve-fit algorithm, calculate up to 120
sets of offset and FSO correcting values.
9) Download correction coefficients to transducer
EEPROM.
10) Perform a final test.
The resulting transducer temperature errors are limited by
the following factors:
Number of selected segments for compensation (up to
120).
Accuracy of the curve fitting, which depends on the
algorithm used, the number of test temperatures, and
the sensor temperature error’s shape.
Repeatability of the sensor performance. This will limit
the MAX1457’s accuracy.
Sensor Calibration and
Compensation Example
Calibration and compensation requirements for a sen-
sor involve conversion of the sensor-specific perfor-
mance into a normalized output curve. An example of
the MAX1457’s capabilities is shown in Table 1.
As shown in Table 1, a repeatable piezoresistive sensor
with an initial offset of 16.4mV and FSO of 55.8mV was
converted into a compensated transducer (utilizing the
piezoresistive sensor with the MAX1457) with an offset
of 0.500V and a span of 4.000V. Nonlinear sensor offset
and FSO temperature errors, which were on the order
of 4% to 5% FSO, were reduced to under ±0.1% FSO.
The graphs in Figure 8 show the output of the uncom-
pensated sensor and the output of the compensated
transducer.
0.1%-Ac c urate S ignal Conditioner
for Piezoresistive S ensor Compensation
10
______________________________________________________________________________________
M
EDO
V
OUT
V
DD
MCS
MODULE 1
E
EDI
ECLK
ECS
V
SS
V
SS
V
DD
V
DD
V
SS
TEST
OVEN
M
EDO
V
OUT
MCS
MODULE 2
E
EDI
ECLK
EDI
EDO
VOUT
ECLK
DIGITAL
MULTIPLEXER
+5V
ECS1
ECS[1:N], MCS[1:N]
ECS2
MCS1
MCS2
ECS N
MCS N
ECS
M
EDO
V
OUT
MCS
MODULE N
E
EDI
ECLK
ECS
DVM
Figure 7. Automated Test System Concept
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