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參數(shù)資料
| 型號： | MAX144BEUA |
| 廠商： | MAXIM INTEGRATED PRODUCTS INC |
| 元件分類： | ADC |
| 英文描述： | +2.7V, Low-Power, 2-Channel, 108ksps, Serial 12-Bit ADCs in 8-Pin レMAX |
| 中文描述： | 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8 |
| 封裝： | MO-187, MICRO MAX PACKAGE-8 |
| 文件頁數(shù)： | 13/16頁 |
| 文件大小： | 240K |
| 代理商： | MAX144BEUA |
Layout, Grounding, and Bypassing
For best performance, use printed circuit boards
(PCBs). Wire-wrap configurations are not recommend-
ed, since the layout should ensure proper separation of
analog and digital traces. Run analog and digital lines
anti-parallel to each other, and don’t lay out digital sig-
nal paths underneath the ADC package. Use separate
analog and digital PCB ground sections with only one
star-point (Figure 11) connecting the two ground systems
(analog and digital). For lowest-noise operation, ensure
the ground return to the star ground’s power supply is
low impedance and as short as possible. Route digital
signals far away from sensitive analog and reference
inputs.
High-frequency noise in the power supply V
DD
could
influence the proper operation of the ADC’s fast com-
parator. Bypass V
DD
to the star ground with a network
of two parallel capacitors (0.1μF and 1μF) located as
close as possible to the power supply pin of MAX144/
MAX145. Minimize capacitor lead length for best sup-
ply-noise rejection and add an attenuation resistor
(10
) if the power supply is extremely noisy.
M
+2.7V, Low-Power, 2-Channel, 108ksps,
S erial 12-Bit ADCs in 8-Pin μMAX
______________________________________________________________________________________
13
CONTROL BIT
MAX144/MAX145
SETTINGS
SYNCHRONOUS SERIAL-PORT STATUS REGISTER (SSPSTAT)
SMP
BIT7
0
SPI Data Input Sample Phase. Input data is sampled at the middle of the data output
time.
CKE
D/A
P
S
R/W
UA
BF
BIT6
BIT5
BIT4
BIT3
BIT2
BIT1
BIT0
1
X
X
X
X
X
X
SPI Clock Edge Select Bit. Data will be transmitted on the rising edge of the serial clock.
Data Address Bit
Stop Bit
Start Bit
Read/Write Bit Information
Update Address
Buffer Full Status Bit
Table 3. Detailed SSPSTAT Register Contents
CHID D11
D10
D9
D8
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
D7
D6
D5
D4
D3
HIGH-Z
DOUT*
CS/SHDN
SCLK
1ST BYTE READ
2ND BYTE READ
SAMPLING INSTANT
*WHEN CS/SHDN IS HIGH, DOUT = HIGH-Z
MSB
LSB
D2
D1
D0
Figure 10b. SPI Interface Timing with PIC16/PIC17 in Master Mode (CKE = 1, CKP = 0, SMP = 0, SSPM3–SSPM0 = 0001)
SCK
SDI
GND
GND
I/O
SCLK
DOUT
CS/SHDN
V
DD
V
DD
MAX144
MAX145
PIC16/17
Figure 10a. SPI Interface Connection for a PIC16/PIC17
Controller
X = Don’t care
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