參數(shù)資料
型號(hào)： MAX1434ECQ+D
廠商： Maxim Integrated Products
文件頁(yè)數(shù)： 9/22頁(yè)
文件大?。?/td> 0K
描述： IC ADC 10BIT 50MSPS 100-TQFP
標(biāo)準(zhǔn)包裝： 90
位數(shù)： 10
采樣率（每秒）： 50M
數(shù)據(jù)接口： LVDS，串行
轉(zhuǎn)換器數(shù)目： 8
功率耗散（最大）： 882mW
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： *
封裝/外殼： 100-TQFP 裸露焊盤
供應(yīng)商設(shè)備封裝： 100-TQFP（14x14）
包裝： 托盤
輸入數(shù)目和類型： 8 個(gè)差分
LVDS and SLVS Signals (SLVS/
LVDS)
Drive SLVS/LVDS low for LVDS or drive SLVS/LVDS high
for SLVS levels at the MAX1434 outputs (OUT_P, OUT_N,
CLKOUTP, CLKOUTN, FRAMEP, and FRAMEN). For
SLVS levels, enable double-termination by driving DT
high. See the
Electrical Characteristics table for LVDS
and SLVS output voltage levels.
LVDS Test Pattern (LVDSTEST)
Drive LVDSTEST high to enable the output test pattern
on all LVDS or SLVS output channels. The output test
pattern is 0001011101. Drive LVDSTEST low for normal
operation (test pattern disabled).
Common-Mode Output (CMOUT)
CMOUT provides a common-mode reference for DC-
coupled analog inputs. If the input is DC-coupled,
match the output common-mode voltage of the circuit
driving the MAX1434 to the output voltage at VCMOUT
to within ±50mV. It is recommended that the output
common-mode voltage of the driving circuit be derived
from CMOUT.
Double-Termination (DT)
The MAX1434 offers an optional, internal 100
termination
between the differential output pairs (OUT_P and OUT_N,
CLKOUTP and CLKOUTN, FRAMEP and FRAMEN).
In addition to the termination at the end of the line, a
second termination directly at the outputs helps eliminate
unwanted reflections down the line. This feature is useful
in applications where trace lengths are long (>5in) or with
mismatched impedance. Drive DT high to select double-
termination, or drive DT low to disconnect the internal ter-
mination resistor (single-termination). Selecting
double-termination increases the OVDD supply current
(see Figure 8).
Power-Down Mode (PD)
The MAX1434 offers a power-down mode to efficiently
use power by transitioning to a low-power state when
conversions are not required.
PD controls the power-down mode of all channels and
the internal reference circuitry. Drive PD high to enable
power-down. In power-down mode, the output imped-
ance of all of the LVDS/SLVS outputs is approximately
342
, if DT is low. The output impedance of the differen-
tial LVDS/SLVS outputs is 100
when DT is high. See the
Electrical Characteristics table for typical supply currents
during power-down. The following list shows the state of
the analog inputs and digital outputs in power-down
mode:
IN_P, IN_N analog inputs are disconnected from
the internal input amplifier
REFIO has > 1M
to GND
OUT_P, OUT_N, CLKOUTP, CLKOUTN, FRAMEP,
and FRAMEN have approximately 342
between
the output pairs when DT is low. When DT is high,
the differential output pairs have 100
between
each pair.
When operating from the internal reference, the wake-
up time from power-down is typically 100ms (CREFP to
GND = CREFN to GND = 1F). When using an external
reference, the wake-up time is dependent on the exter-
nal reference drivers.
Applications Information
Full-Scale Range Adjustments
Using the Internal Reference
The MAX1434 supports a full-scale adjustment range of
10% (±5%). To decrease the full-scale range, add a
25k
to 250k external resistor or potentiometer (RADJ)
between REFADJ and GND. To increase the full-scale
range, add a 25k
to 250k resistor between REFADJ
and REFIO. Figure 9 shows the two possible configura-
tions.
The following equations provide the relationship between
RADJ and the change in the analog full-scale range:
for RADJ connected between REFADJ and REFIO, and:
FSR
V
k
RADJ
=+
07
1
125
.
MAX1434
Octal, 10-Bit, 50Msps, 1.8V ADC
with Serial LVDS Outputs
______________________________________________________________________________________
17
MAX1434
100
100
OUT_P/
CLKOUTP/
FRAMEP
OUT_N/
CLKOUTN/
FRAMEN
DT
SWITCHES ARE CLOSED WHEN DT IS HIGH.
SWITCHES ARE OPEN WHEN DT IS LOW.
Z0 = 50
Z0 = 50
Figure 8. Double-Termination
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