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參數(shù)資料
| 型號： | MAX1430 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | ADC |
| 英文描述： | 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications |
| 中文描述： | 15位、100Msps ADC，具有-76.8dBFS的噪聲底，適合IF系統(tǒng) |
| 文件頁數(shù)： | 8/18頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MAX1430 |
M
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applic ations
8
_______________________________________________________________________________________
Pin Desc ription
PIN
NAME
FUNCTION
1, 2, 3, 6, 9, 12, 14–17,
20, 23, 26, 27, 30, 52–56, EP
GND
Converter Ground. Analog, digital, and output driver grounds are internally
connected to the same potential. Connect the converter’s EP to GND.
4
5
CLKP
CLKN
Differential Clock, Positive Input Terminal
Differential Clock, Negative Input Terminal
7, 8, 18, 19, 21, 22, 24, 25, 28
AV
CC
Analog Supply Voltage. Provide local bypassing to ground with 0.1μF to 0.22μF
capacitors.
10
11
13
INP
INN
CM
Differential Analog Input, Positive Terminal
Differential Analog Input, Negative/Complementary Terminal
Common-Mode Reference Terminal
29
DV
CC
Digital Supply Voltage.
Provide local bypassing to ground with 0.1μF to 0.22μF
capacitors.
31, 41, 42, 51
DRV
CC
Digital Output Driver Supply Voltage. Provide local bypassing to ground with
0.1μF to 0.22μF capacitors.
32
DOR
Data Overrange Bit. This control line flags an overrange condition in the ADC.
If DOR transitions high, an overrange condition is detected. If DOR remains low, the
ADC operates within the allowable full-scale range.
33
34
35
36
37
38
39
40
43
44
45
46
47
48
49
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
D10
D11
D12
D13
D14
Digital CMOS Output Bit 0 (LSB)
Digital CMOS Output Bit 1
Digital CMOS Output Bit 2
Digital CMOS Output Bit 3
Digital CMOS Output Bit 4
Digital CMOS Output Bit 5
Digital CMOS Output Bit 6
Digital CMOS Output Bit 7
Digital CMOS Output Bit 8
Digital CMOS Output Bit 9
Digital CMOS Output Bit 10
Digital CMOS Output Bit 11
Digital CMOS Output Bit 12
Digital CMOS Output Bit 13
Digital CMOS Output Bit 14 (MSB)
50
DAV
Data Valid Output. This output can be used as a clock control line to drive an
external buffer or data-acquisition system. The typical delay time between the
falling edge of the converter clock and the rising edge of DAV is 6.5ns.
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