參數(shù)資料
型號(hào): MAX1428
廠商: Maxim Integrated Products, Inc.
英文描述: 15-Bit, 80Msps ADC with -78.4dBFS Noise Floor for IF Applications
中文描述: 15位、80Msps ADC,具有-78.4dBFS的噪底,適合IF系統(tǒng)
文件頁(yè)數(shù): 9/18頁(yè)
文件大?。?/td> 717K
代理商: MAX1428
M
15-Bit, 80Msps ADC with -78.4dBFS
Noise Floor for IF Applications
_______________________________________________________________________________________
9
Detailed Description
Figure 1 provides an overview of the MAX1428 archi-
tecture. The MAX1428 employs an input T/H amplifier,
which has been optimized for low thermal noise and
low distortion. The high-impedance differential inputs to
the T/H amplifier (INP and INN) are self-biased at
4.163V, and support a full-scale differential input volt-
age of 2.56V
P-P
. The output of the T/H amplifier is fed to
a multistage pipelined ADC core, which has also been
optimized to achieve a very low thermal noise floor and
low distortion.
A clock buffer receives a differential input clock wave-
form and generates a low-jitter clock signal for the input
T/H. The signal at the analog inputs is sampled at the
rising edge of the differential clock waveform. The dif-
ferential clock inputs (CLKP and CLKN) are high-
impedance inputs, are self-biased at 2.4V, and support
differential clock waveforms from 0.5V
P-P
to 3.0V
P-P
.
The outputs from the multistage pipelined ADC core
are delivered to error correction and formatting logic,
which in turn, deliver the 15-bit output code in two’s-
complement format to digital output drivers. The output
drivers provide CMOS-compatible outputs with levels
programmable over a 2.3V to 3.5V range.
Analog Inputs and
Common Mode (INP, INN, CM)
The signal inputs to the MAX1428 (INP and INN) are
balanced differential inputs. This differential configura-
tion provides immunity to common-mode noise cou-
pling and rejection of even-order harmonic terms. The
differential signal inputs to the MAX1428 should be AC-
coupled and carefully balanced to achieve the best
dynamic performance (see the
Applications Information
section for more detail). AC-coupling of the input signal
is easily accomplished because the MAX1428 inputs
are self-biasing as illustrated in Figure 2. Although the
T/H inputs are high impedance, the actual differential
input impedance is nominally 1k
because of the two
500
bias resistors connected from each input to the
common-mode reference.
The CM pin provides a monitor of the input common-
mode self-bias potential. In most applications, in which
the input signal is AC-coupled, this pin is not connect-
ed. If DC-coupling of the input signal is required, this
pin may be used to construct a DC servo loop to con-
trol the input common-mode potential. See the
Applications Information
section for more details.
T/H
CORRECTION
LOGIC + OUTPUT
BUFFERS
INTERNAL
TIMING
INTERNAL
REFERENCE
INP
INN
CM
CLKP
CLKN
DAV
15
DATA BITS D0 THROUGH D14
AV
CC
DRV
CC
DV
CC
GND
MULTISTAGE
PIPELINE ADC CORE
CLOCK
BUFFER
MAX1428
Figure 1. Simplified MAX1428 Diagram
BUFFER
INTERNAL REFERENCE
AND BIASING CIRCUIT
T/H AMPLIFIER
T/H AMPLIFIER
500
500
CM
INP
INN
TO 1. QUANTIZER STAGE
TO 1. QUANTIZER STAGE
1k
Figure 2. Simplified Analog and Common-Mode Input Architecture
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