參數(shù)資料
型號(hào)： MAX1427
廠商： Maxim Integrated Products, Inc.
英文描述： 15-Bit, 65Msps ADC with -78.2dBFS Noise Floor for IF Applications
中文描述： 15位、80Msps ADC，具有-79.3dBFS的噪聲底，適合基帶系統(tǒng)
文件頁(yè)數(shù)： 12/20頁(yè)
文件大小： 352K
代理商： MAX1427
M
15-Bit, 65Msps ADC with -78.2dBFS
Noise Floor for IF Applications
12
______________________________________________________________________________________
On-Chip Reference Circuit
The MAX1418 incorporates an on-chip 2.5V, low-drift
bandgap reference. This reference potential establish-
es the full-scale range for the converter, which is nomi-
nally 2.56V
P-P
differential. The internal reference
potential is not accessible to the user, so the full-scale
range for the MAX1418 cannot be externally adjusted.
Figure 3 shows how the reference is used to generate
the common-mode bias potential for the analog inputs.
The common-mode input bias is set to two diode poten-
tials above the bandgap reference potential, and so
varies over temperature.
Clock Inputs (CLKP, CLKN)
The differential clock buffer for the MAX1418 has been
designed to accept an AC-coupled clock waveform. Like
the signal inputs, the clock inputs are self-biasing. In this
case, the common-mode bias potential is 2.4V and each
input is connected to the reference potential through a
1k
resistor. Consequently, the differential input resis-
tance associated with the clock inputs is 2k
. While dif-
ferential clock signals as low as 0.5V
P-P
may be used to
drive the clock inputs, best dynamic performance is
achieved with clock input voltage levels of 2V
P-P
to 3V
P-P
.
Jitter on the clock signal translates directly to jitter (noise)
on the sampled signal. Therefore, the clock source
should be a low-jitter (low phase noise) source. See the
Applications Information
section for additional details on
driving the clock inputs.
System Timing Requirements
Figure 4 depicts the timing relationships for the signal
input, clock input, data output, and DAV output. The
variables shown in the figure correspond to the various
timing specifications in the
Electrical Characteristics
section. These include:
t
DAT
: Delay from the rising edge of the clock until the
50% point of the output data transition
t
DAV
: Delay from the falling edge of the clock until the
50% point of the DAV rising edge
t
DNV
: Time from the rising edge of the clock until data
is no longer valid
t
DGV
: Time from the rising edge of the clock until data
is guaranteed to be valid
1mA
2mA
INP/INN
COMMON-MODE
REFERENCE
500
500
1k
2.5V
Figure
3. Simplified Reference Architecture
INP
INN
D0–D14
DOR
DAV
N + 1
N
N + 2
N + 3
CLKP
CLKN
t
AD
t
CLKP
t
CLKN
N - 3
N - 2
N - 1
N
t
S
t
H
t
DAT
t
DAV
t
DNV
t
DGV
Figure
4. System and Output Timing Diagram
相關(guān)PDF資料
PDF描述
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MAX1427ETN+ 制造商:Maxim from Components Direct 功能描述:THE MAXIM MAX1427ETN+ IS AN ANALOG TO DIGITAL CONVERTER. - Rail/Tube 制造商:Maxim Integrated Products 功能描述:- Rail/Tube 制造商:Maxim 功能描述:Maxim MAX1427ETN+, 15bit Analog-to-Digital Converter 5V 80Msps -79.dBFS 56-pin TQFN
MAX1427ETN+TD 制造商:Maxim Integrated Products 功能描述:- Tape and Reel
MAX1427ETN-D 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1427ETN-TD 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類(lèi)型:Differential 信噪比:107 dB 接口類(lèi)型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32
MAX1427EVKIT 功能描述:數(shù)據(jù)轉(zhuǎn)換 IC 開(kāi)發(fā)工具 RoHS:否 制造商:Texas Instruments 產(chǎn)品:Demonstration Kits 類(lèi)型:ADC 工具用于評(píng)估:ADS130E08 接口類(lèi)型:SPI 工作電源電壓:- 6 V to + 6 V
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