
MAX1421
12-Bit, 40Msps, 3.3V, Low-Power ADC
with Internal Reference
4
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD = VDVDD = 3.3V, AGND = DGND = 0, VIN = ±1.024V, differential input voltage at -0.5dB FS, internal reference,
fCLK = 40MHz (50% duty cycle), digital output load CL
≈ 10pF, TA ≥ +25°C guaranteed by production test, TA < +25°C guarnateed
by design and characterization. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Differential Reference Voltage
Range
VDIFF
(Note 6)
1.024
±10%
V
CML Input Voltage Range
VCML
1.65
±10%
V
REFP Input Voltage Range
VREFP
VCML +
VDIFF / 2
V
REFN Input Voltage Range
VREFN
VCML -
VDIFF / 2
V
DIGITAL INPUTS (CLK,
CLK, OE, PD)
Input Logic-High
VIH
0.7
VDVDD
V
Input Logic-Low
VIL
0.3
VDVDD
V
CLK, CLK
±330
PD
-20
+20
Input Current
OE
-20
+20
A
Input Capacitance
10
pF
DIGITAL OUTPUTS (D0–D11)
Output Logic-High
VOH
IOH = 200A
VDVDD
- 0.5
VDVDD
V
Output Logic-Low
VOL
IOL = -200A
0
0.5
V
Three-State Leakage
-10
+10
A
Three-State Capacitance
2pF
POWER REQUIREMENTS
Analog Supply Voltage
VAVDD
3.135
3.3
3.465
V
Digital Supply Voltage
VDVDD
2.7
3.3
3.6
V
Analog Supply Current
IAVDD
52
65
mA
Analog Supply Current with
Internal Reference in Shutdown
REFIN = AGND
50
63
mA
Analog Shutdown Current
PD = DVDD
20
A
Digital Supply Current
IDVDD
5.5
mA
Digital Shutdown Current
PD = DVDD
20
A
Power Dissipation
PDISS
Analog power
188
214
mW
Power-Supply Rejection Ratio
PSRR
(Note 9)
±1
mV/V
TIMING CHARACTERISTICS
Clock Frequency
fCLK
Figure 5
0.1
40.0
MHz
Clock High
tCH
Figure 5, clock period 25ns
12.5
ns
Clock Low
tCL
Figure 5, clock period 25ns
12.5
ns