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參數(shù)資料
| 型號(hào)： | MAX1419 |
| 廠商： | Maxim Integrated Products, Inc. |
| 元件分類： | ADC |
| 英文描述： | 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications |
| 中文描述： | 15位、65Msps ADC，具有-79.3dBFS的噪底，適合基帶系統(tǒng) |
| 文件頁數(shù)： | 12/18頁 |
| 文件大?。?/td> | 219K |
| 代理商： | MAX1419 |
M
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applic ations
12
______________________________________________________________________________________
Applic ations Information
Differential, AC-Coupled Cloc k Input
The clock inputs to the MAX1429 are designed to be
driven with an AC-coupled differential signal, and best
performance is achieved under these conditions.
However, it is often the case that the available clock
source is single ended. Figure 5 demonstrates one
method for converting a single-ended clock signal into
a differential signal through a transformer. In this exam-
ple, the transformer turns ratio from the primary to sec-
ondary side is 1:1.414. The impedance ratio from
primary to secondary is the square of the turns ratio, or
1:2, so that terminating the secondary side with a 100
differential resistance results in a 50
load looking into
the primary side of the transformer. The termination
resistor in this example comprises the series combina-
tion of two 50
resistors with their common node AC-
coupled to ground. Alternatively, a single 100
resistor
across the two inputs with no common-mode connec-
tion could be employed.
In the example of Figure 5, the secondary side of the
transformer is coupled directly to the clock inputs.
Since the clock inputs are self-biasing, the center tap of
the transformer must be AC-coupled to ground or left
floating. If the center tap of the secondary were DC-
coupled to ground, then it would be necessary to add
blocking capacitors in series with the clock inputs.
Clock jitter is generally improved if the clock signal has
a high slew rate at the time of its zero crossing.
Therefore, if a sinusoidal source is used to drive the
clock inputs, it is desirable that the clock amplitude be
as large as possible to maximize the zero-crossing
slew rate. The back-to-back Schottky diodes shown in
Figure 5 are not required as long as the input signal is
held to 3V
P-P
differential or less. If a larger amplitude
signal is provided (to maximize the zero-crossing slew
rate), then the diodes serve to limit the differential sig-
nal swing at the clock inputs.
Any differential mode noise coupled to the clock inputs
translates to clock jitter and degrades the SNR perfor-
mance of the MAX1429. Any differential mode coupling
of the analog input signal into the clock inputs results in
harmonic distortion. Consequently, it is important that
the clock lines be well isolated from the analog signal
input and from the digital outputs. See the
PC Board
Layout Considerations
sections for more discussion on
noise coupling.
Differential, AC-Coupled Analog Input
The analog inputs (INP and INN) are designed to be dri-
ven with a differential AC-coupled signal. It is extremely
important that these inputs be accurately balanced. Any
common-mode signal applied to these inputs degrade
even-order distortion terms. Therefore, any attempt at
driving these inputs in a single-ended fashion results in
significant even-order distortion terms.
Figure 6 presents one method for converting a single-
ended signal to a balanced differential signal using a
transformer. The primary-to-secondary turns ratio in this
example is 1:1.414. The impedance ratio is the square
of the turns ratio, so in this example, the impedance
ratio is 1:2. In order to achieve a 50
input impedance
at the primary side of the transformer, the secondary
side is terminated with a 112
differential load. This
load, in shunt with the differential input resistance of the
MAX1429, results in a 100
differential load on the sec-
ondary side. It is reasonable to use a larger transformer
turns ratio in order to achieve a larger signal step-up,
and this may be desirable in order to relax the drive
requirements for the circuitry driving the MAX1429.
MAX1429
50
50
0.1
μ
F
0.1
μ
F
0.01
μ
F 0.1
μ
F
0.01
μ
F
BACK-TO-BACK DIODE
T2-1T–KK81
15
D0–D14
AV
CC
DV
CC
DRV
CC
GND
CLKP
CLKN
INP
INN
Figure 5. Transformer-Coupled Clock Input Configuration
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參數(shù)描述 |
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| MAX1419ETN+D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1419ETN+TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1419ETN-D | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1419ETN-TD | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX141CQH-C10006 | 制造商:Maxim Integrated Products 功能描述:MXMMAX141CQH-C10006 ADC - CUSTOMIZED |
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