參數(shù)資料
型號: MAX1418ETN
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 15-Bit, 65Msps ADC with -78.2dBFS Noise Floor for IF Applications
中文描述: 1-CH 15-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56
封裝: 8 X 8 MM, 0.80 MM HEIGHT, MO-220WLLD-5, TQFN-56
文件頁數(shù): 10/18頁
文件大?。?/td> 219K
代理商: MAX1418ETN
M
15-Bit, 100Msps ADC with -77.7dBFS
Noise Floor for Baseband Applic ations
10
______________________________________________________________________________________
On-Chip Referenc e Circ uit
The MAX1429 incorporates an on-chip 2.5V, low-drift
bandgap reference. This reference potential establish-
es the full-scale range for the converter, which is nomi-
nally 2.2V
P-P
differential. The internal reference
potential is not accessible to the user, so the full-scale
range for the MAX1429 cannot be externally adjusted.
Figure 3 shows how the reference is used to generate
the common-mode bias potential for the analog inputs.
The common-mode input bias is set to one diode
potential above the bandgap reference potential, and
so varies over temperature.
Cloc k Inputs (CLK P, CLK N)
The differential clock buffer for the MAX1429 has been
designed to accept an AC-coupled clock waveform.
Like the signal inputs, the clock inputs are self-biasing.
In this case, the common-mode bias potential is 2.4V
and each input is connected to the reference potential
through a 1k
resistor. Consequently, the differential
input resistance associated with the clock inputs is
2k
. While differential clock signals as low as 0.5V
P-P
may be used to drive the clock inputs, best dynamic
performance is achieved with clock input voltage levels
of 2V
P-P
to 3V
P-P
. J itter on the clock signal translates
directly to jitter (noise) on the sampled signal.
Therefore, the clock source should be a low-jitter (low-
phase noise) source. See the
Applications Information
section for additional details on driving the clock inputs.
S ystem T iming Requirements
Figure 4 depicts the timing relationships for the signal
input, clock input, data output, and DAV output. The
variables shown in the figure correspond to the various
timing specifications in the
Electrical Characteristics
table. These include:
t
DAT
: Delay from the rising edge of the clock until the
50% point of the output data transition
t
DAV
: Delay from the falling edge of the clock until the
50% point of the DAV rising edge
t
DNV
: Time from the rising edge of the clock until data
is no longer valid
1mA
2mA
INP/INN
COMMON-MODE
REFERENCE
500
500
1k
2.5V
Figure 3. Simplified Reference Architecture
INP
INN
D0–D14
DOR
DAV
N + 1
N
N + 2
N + 3
CLKP
CLKN
t
AD
t
CLKP
t
CLKN
N - 3
N - 2
N - 1
N
t
S
t
H
t
DAT
t
DAV
t
DNV
t
DGV
Figure 4. System and Output Timing Diagram
相關(guān)PDF資料
PDF描述
MAX1419ETN 15-Bit, 65Msps ADC with -79.3dBFS Noise Floor for Baseband Applications
MAX1429 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications
MAX1429ETN 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications
MAX1430 15-Bit, 100Msps ADC with -77.7dBFS Noise Floor for Baseband Applications
MAX1444 10-Bit, 40Msps, 3.0V, Low-Power ADC with Internal Reference
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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