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    參數(shù)資料
    型號: MAX1415EWE
    廠商: MAXIM INTEGRATED PRODUCTS INC
    元件分類: ADC
    英文描述: 16-Bit, Low-Power, 2-Channel, Sigma-Delta ADCs
    中文描述: 2-CH 16-BIT DELTA-SIGMA ADC, SERIAL ACCESS, PDSO16
    封裝: 0.300 INCH, MS-013AA, SOIC-16
    文件頁數(shù): 5/36頁
    文件大?。?/td> 669K
    代理商: MAX1415EWE
    M
    16-Bit, Low-Power, 2-Channel,
    Sigma-Delta ADCs
    _______________________________________________________________________________________
    5
    ELECTRICAL CHARACTERISTICS—MAX1415 (continued)
    (V
    DD
    = 3V, GND = 0, V
    REF+
    = 1.225V, V
    REF-
    = GND, external f
    CLKIN
    = 2.4576MHz, CLKDIV bit = 0, C
    REF+
    to GND = 0.1μF, C
    REF-
    to
    GND = 0.1μF, T
    A
    = T
    MIN
    to T
    MAX
    , unless otherwise noted.)
    PARAMETER
    SYMBOL
    CONDITIONS
    MIN
    TYP
    MAX
    UNITS
    Typical Conversion-Time
    Variation
    t
    CONV
    t
    CONV
    = 1/ODR
    ±0.5
    %
    ELECTRICAL CHARACTERISTICS—MAX1416
    (V
    DD
    = 5V, GND = 0, V
    REF+
    = 2.5V, V
    REF-
    = GND, f
    CLKIN
    = 2.4576MHz, CLKDIV bit = 0, C
    REF+
    to GND = 0.1μF, C
    REF-
    to GND =
    0.1μF, T
    A
    = T
    MIN
    to T
    MAX
    , unless otherwise noted.)
    PARAMETER
    SYMBOL
    CONDITIONS
    MIN
    TYP
    MAX
    UNITS
    DC ACCURACY
    Resolution (No Missing Codes)
    Output Noise
    Integral Nonlinearity
    Unipolar Offset Error
    Unipolar Offset Drift
    Bipolar Zero Error
    16
    Bits
    μV
    %FSR
    μV
    μV/°C
    μV
    (Tables 1, 3)
    INL
    Gain = 1, bipolar mode, unbuffered
    After calibration
    (Note 2)
    After calibration
    Gain = 1 to 4
    Gain = 8 to 128
    ±
    0.0015
    (Note 1)
    0.5
    (Note 1)
    0.5
    0.1
    Bipolar Zero Drift (Note 2)
    μV/°C
    TIMING CHARACTERISTICS—MAX1415
    (Note 16) (Figures 8, 9)
    PARAMETER
    SYMBOL
    CONDITIONS
    MIN
    TYP
    MAX
    UNITS
    DRDY
    High Time
    500/
    f
    CLKIN
    100
    0
    120
    0
    100
    100
    0
    s
    Reset Pulse-Width Low
    DRDY
    Fall to
    CS
    Fall Setup Time
    CS
    Fall to SCLK Rise Setup Time
    SCLK Fall to DOUT Valid Delay
    SCLK Pulse-Width High
    SCLK Pulse-Width Low
    CS
    Rise to SCLK Rise Hold Time
    ns
    ns
    ns
    ns
    ns
    ns
    ns
    t
    1
    t
    2
    t
    3
    t
    4
    t
    5
    t
    6
    100
    Bus Relinquish Time After SCLK
    Rising Edge
    t
    7
    100
    ns
    SCLK Fall to
    DRDY
    Rise Delay
    DIN to SCLK Setup Time
    DIN to SCLK Hold Time
    t
    8
    t
    9
    t
    10
    100
    ns
    ns
    ns
    30
    20
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