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參數(shù)資料
| 型號： | MAX1400CAI+ |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 6/34頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 18BIT LP 28-SSOP |
| 產(chǎn)品培訓模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標準包裝： | 46 |
| 位數(shù)： | 18 |
| 采樣率（每秒）： | 480 |
| 數(shù)據(jù)接口： | QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.25mW |
| 電壓電源： | 模擬和數(shù)字 |
| 工作溫度： | 0°C ~ 70°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 28-SSOP（0.209"，5.30mm 寬） |
| 供應商設備封裝： | 28-SSOP |
| 包裝： | 管件 |
| 輸入數(shù)目和類型： | 3 個差分，單極；3 個差分，雙極；5 個偽差分，單極；5 個偽差分，雙極 |
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MAX1400
+5V, 18-Bit, Low-Power, Multichannel,
Oversampling (Sigma-Delta) ADC
14
______________________________________________________________________________________
FSYNC: (Default = 0) Filter Sync Bit. When FSYNC = 0,
conversions are automatically performed at a data rate
determined by CLK, FS1, FS0, MF1, and MF0 bits.
When FSYNC = 1, the digital filter and analog modulator
are held in reset, inhibiting normal self-timed operation.
This bit may be used to convert on command to mini-
mize the settling time to valid output data, or to synchro-
nize operation of a number of MAX1400s. FSYNC does
not reset the serial interface or the 0/DRDY flag. To clear
the 0/DRDY flag while FSYNC is active, simply read the
data register.
Global Setup Register 1
A1, A0: (Default = 0, 0) Channel-Selection Control Bits.
These bits (combined with the state of the DIFF, M1,
and M0 bits) determine the channel selected for con-
version according to Tables 8, 9, and 10. These bits
are ignored if the SCAN bit is set.
MF1, MF0: (Default = 0, 0) Modulator Frequency Bits.
MF1 and MF0 determine the ratio of CLKIN oscillator fre-
quency to modulator operating frequency. They affect
the output data rate, the position of the digital filter notch
frequencies, and the power dissipation of the device.
Achieve lowest power dissipation with MF1 = 0 and MF0
= 0. Highest power dissipation and fastest output data
rate occur with these bits set to 1, 1 (Table 2).
CLK: (Default = 1) CLK Bit. The CLK bit is used in con-
junction with X2CLK to tell the MAX1400 the frequency
of the CLKIN input signal. If CLK = 0, a CLKIN input fre-
quency of 1.024MHz (2.048MHz for X2CLK = 1) is
expected. If CLK = 1, a CLKIN input frequency of
2.4576MHz (4.1952MHz for X2CLK = 1) is expected.
This bit affects the decimation factor in the digital filter
and thus the output data rate (Table 2).
FS1, FS0: (Default = 0, 1) Filter Selection Bits. These
bits (in conjunction with the CLK bit) control the deci-
mation ratio of the digital filter. They determine the out-
put data rate, the position of the digital filter-frequency
response notches, and the noise present in the output
result. (Table 2).
FAST: (Default 0) FAST Bit. FAST = 0 causes the digi-
tal filter to perform a SINC3 filter function on the modu-
lator data stream. The output data rate will be
determined by the values in the CLK, FS1, FS0, MF1,
and MF0 bits (Table 2). The settling time for SINC3
function is 3 [1 / (output data rate)]. In SINC3 mode, the
MAX1400 automatically holds the DRDY signal false
(after any significant configuration change) until settled
data is available. FAST = 1 causes the digital filter to
perform a SINC1 filter function on the modulator data
stream. The signal-to-noise ratio achieved with this filter
function is less than that of the SINC3 filter; however
SINC1 settles in a single output sample period, rather
than a minimum of three output sample periods for
SINC3. When switching from SINC1 to SINC3 mode, the
DRDY flag will be deasserted and reasserted after the
filter has fully settled. This mode change requires a
minimum of three samples.
Global Setup Register 2
SCAN: (Default = 0) Scan Bit. Setting this bit to a 1
causes sequential scanning of the input channels as
determined by DIFF, M1, and M0 (see Scanning
(SCAN-mode) section). When SCAN = 0, the MAX1400
repeatedly measures the unique channel selected by
A1, A0, DIFF, M1, and M0.
M1, M0: (Default 0, 0) Mode Control Bits. These bits
control access to the calibration channels CALOFF and
CALGAIN. When SCAN = 0, setting M1 = 0 and M0 = 1
selects the CALOFF input, and M1 = 1 and M0 = 0
selects the CALGAIN input (Table 3). When SCAN = 1
and M1
≠ M0, the scanning sequence includes both
CALOFF and CALGAIN inputs (Table 4). When SCAN is
set to 1 and the device is scanning the available input
First Bit (MSB)
(LSB)
First Bit (MSB)
(LSB)
A1
CLK
0
1
A0
Defaults
CHANNEL SELECTION
0
MF1
0
MF0
MODULATOR
FREQUENCY
0
FAST
Name
0
FS1
0
FS0
FILTER SELECTION
1
FUNCTION
SCAN
DIFF
0
M1
Defaults
0
M0
0
BUFF
MODE CONTROL
0
X2CLK
Name
0
BOUT
0
RESERVED
0
FUNCTION
Global Setup Register 2
Global Setup Register 1
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1400CAI+ | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 5Ch 4.8ksps 2.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1400CAI+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 18-Bit 5Ch 4.8ksps 2.5V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1400CAI+W | 制造商:Maxim Integrated Products 功能描述: |
| MAX1400CAI-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1400EAI | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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