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參數(shù)資料
| 型號(hào)： | MAX1392ETB+T |
| 廠商： | Maxim Integrated Products |
| 文件頁(yè)數(shù)： | 2/18頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | IC ADC 10BIT SAR 10-TDFN |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 357k |
| 數(shù)據(jù)接口： | DSP，MICROWIRE?，QSPI?，串行，SPI? |
| 轉(zhuǎn)換器數(shù)目： | 1 |
| 功率耗散（最大）： | 1.48W |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-WFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-TDFN-EP（3x3） |
| 包裝： | 標(biāo)準(zhǔn)包裝 |
| 輸入數(shù)目和類型： | * |
| 其它名稱： | MAX1392ETB+TDKR |
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MAX1392/MAX1395
Applications Information
Starting a Conversion
A falling edge on CS initiates the power-up sequence
and begins acquiring the analog input as long as OE is
also asserted low. On the 3rd SCLK falling edge, the
analog input is held for conversion. The most significant
bit (MSB) decision is made and clocked onto DOUT on
the 4th SCLK falling edge. Valid DOUT data is available
to be clocked into the master (microcontroller (C)) on
the following SCLK rising edge. The rest of the bits are
decided and clocked out to DOUT on each successive
SCLK falling edge. See Figures 8 and 9 for conversion
timing diagrams.
Once a conversion has been initiated, CS can go high at
any time. Further falling edges of CS do not reinitiate an
acquisition cycle until the current conversion completes.
Once a conversion completes, the first falling edge of CS
begins another acquisition/conversion cycle.
Selecting Unipolar or Bipolar Mode
(MAX1392 Only)
Drive UNI/BIP high to select unipolar mode or pull
UNI/BIP low to select bipolar mode. UNI/BIP can be
connected to VDD for logic high, to GND for logic low,
or actively driven. UNI/BIP needs to be stable for tUBS
prior to the first rising edge of SCLK after the CS falling
edge (see Figure 1) for a valid conversion result when
being actively driven.
Selecting Analog Input AIN1 or AIN2
(MAX1395 Only)
Pull CH1/CH2 low to select AIN1 or drive CH1/CH2
high to select AIN2 for conversion. CH1/CH2 can be
connected to VDD for logic high, to GND for logic low,
or actively driven. CH1/CH2 needs to be stable for tCHS
prior to the first rising edge of SCLK after the CS falling
edge (see Figure 1) for a valid conversion result when
being actively driven.
10
______________________________________________________________________________________
1.5V to 3.6V, 357ksps, 1-Channel True-Differential/
2-Channel Single-Ended, 10-Bit, SAR ADCs
ZS = 0
FS = VREF
1 LSB =
VREF
1024
FS
3FF
3FE
3FC
3FB
000
001
003
004
OUTPUT
CODE
(hex)
INPUT VOLTAGE (LSB)
3FD
0
1234
FS - 1.5 LSB
FULL-SCALE
TRANSITION
002
Figure 5. Unipolar Transfer Function
ZS = 0
+FS =
VREF
2
-FS =
-VREF
2
1 LSB =
VREF
1024
-FS
+FS
1FF
1FE
001
000
200
201
3FE
OUTPUT
CODE
(hex)
INPUT VOLTAGE (LSB)
3FF
0
+FS - 1.5 LSB
-FS + 0.5 LSB
FULL-SCALE
TRANSITION
Figure 6. Bipolar Transfer Function
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MAX1392MTB-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1393ETB | 制造商:Maxim Integrated Products 功能描述:1.5V-3.6V312.5KSPS1-CHANNEL TRUE- - Rail/Tube |
| MAX1393ETB+ | 制造商:Maxim Integrated Products 功能描述:ADC SGL SAR 312.5KSPS 12-BIT SERL 10TDFN EP - Rail/Tube |
| MAX1393ETB+T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC 12-Bit 312ksps 3.6V Precision ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
| MAX1393ETB-T | 功能描述:模數(shù)轉(zhuǎn)換器 - ADC RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 結(jié)構(gòu):Sigma-Delta 轉(zhuǎn)換速率:125 SPs to 8 KSPs 分辨率:24 bit 輸入類型:Differential 信噪比:107 dB 接口類型:SPI 工作電源電壓:1.7 V to 3.6 V, 2.7 V to 5.25 V 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:VQFN-32 |
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