100/120
參數(shù)資料
型號: MAX13451EAUD+
廠商: Maxim Integrated Products
文件頁數(shù): 13/17頁
文件大?。?/td> 0K
描述: TXRX RS-485 14TSSOP
產(chǎn)品培訓模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標準包裝: 96
類型: 收發(fā)器
驅動器/接收器數(shù): 1/1
規(guī)程: RS485
電源電壓: 4.5 V ~ 5.5 V
安裝類型: 表面貼裝
封裝/外殼: 14-TSSOP (0.173",4.40mm 寬)裸露焊盤
供應商設備封裝: 14-TSSOP-EP
包裝: 管件
RS-485 Transceivers with Integrated
100/120 Termination Resistors
MAX13450E/MAX13451E
_______________________________________________________________________________________ 5
SWITCHING CHARACTERISTICS—SRL = LOW
(VCC = +4.5V to +5.5V, VL = +1.62V to VCC, TA = TMIN to TMAX, unless otherwise noted. Typical values are at VCC = +5V,
VL = +1.8V, and TA = +25NC.) (Note 2)
Note 2: All devices are 100% production tested at TA = +25°C. Limits over temperature are guaranteed by design.
Note 3: Termination resistance is disabled (TERM = high).
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
DRIVER
Driver Propagation Delay
tDPLH
RDIFF = 54I, CL = 50pF, Figures 2 and 3
50
ns
tDPHL
50
Differential Driver Output Skew
|tDPLH - tDPHL|
tDSKEW
RDIFF = 54I, CL = 50pF, Figure 3
6
ns
Driver Differential Output Rise or
Fall Time
tHL, tLH
RDIFF = 54I, CL = 50pF, Figures 2 and 3
15
ns
Maximum Data Rate
DRMAX
20
Mbps
Driver Enable from Shutdown to
Output High
tDZH(SHDN)
S2 closed, RL = 500I, CL = 100pF,
Figures 4 and 5
2000
ns
Driver Enable from Shutdown to
Output Low
tDZL(SHDN)
S1 closed, RL = 500I, CL = 100pF,
Figures 4 and 5
2000
ns
Driver Disable Delay
tDLZ, tDHZ Figures 4 and 5
100
ns
Driver Enable Delay
tDZL, tDZH Figures 4 and 5
100
ns
RECEIVER
Receiver Propagation Delay
tRPLH
CL = 15pF, |VID| R 2.0V; tLH, tHL P 15ns,
Figures 6 and 7
50
ns
tRPHL
50
Receiver Output Skew
tRSKEW
CL = 15pF, Figures 6 and 7
6
ns
Maximum Data Rate
DRMAX
20
Mbps
Receiver Enable to Output High
tRZH
S2 closed, CL = 100pF, RL = 500I,
Figures 8 and 9
50
ns
Receiver Enable to Output Low
tRZL
S1 closed, CL = 100pF, RL = 500I,
Figures 8 and 9
50
ns
Receiver Disable Time from High
tRHZ
Figures 8 and 9
50
ns
Receiver Disable Time from Low
tRLZ
Figures 8 and 9
50
ns
Receiver Enable from Shutdown
to Output High
tRZH(SHDN) Figures 8 and 9
2000
ns
Receiver Enable from Shutdown
to Output Low
tRZL(SHDN) Figures 8 and 9
2000
ns
TERMINATION RESISTOR
Turn-Off Time
tRTZ
Figure 10
120
F
s
Turn-On Time
tRTEN
Figure 10
1
F
s
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