參數(shù)資料
型號(hào): MAX1333ETE
廠商: MAXIM INTEGRATED PRODUCTS INC
元件分類: ADC
英文描述: 3Msps/2Msps, 5V/3V, 2-Channel, True-Differential 12-Bit ADCs
中文描述: 2-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, QCC16
封裝: 3 X 3 MM, 0.8 MM HEIGHT, MO-220, TQFN-16
文件頁數(shù): 14/25頁
文件大小: 379K
代理商: MAX1333ETE
M
of interest, lowpass or bandpass filtering is recom-
mended to limit the bandwidth of the input signal.
Input Buffer
To improve the input signal bandwidth under AC condi-
tions, drive the input with a wideband buffer (>50MHz)
that can drive the ADC’s input capacitance (14pF) and
settle quickly. Most applications require an input buffer
to achieve 12-bit accuracy. Although slew rate and
bandwidth are important, the most critical input buffer
specification is settling time. The sampling requires an
acquisition time of 52μs for the MAX1332 and 78μs for
the MAX1333. At the beginning of the acquisition, the
ADC internal sampling capacitors connect to the ana-
log inputs, causing some disturbance. Ensure the
amplifier is capable of settling to at least 12-bit accura-
cy during this interval. Use a low-noise, low-distortion,
wideband amplifier that settles quickly and is stable
with the ADC’s 14pF input capacitance.
See the Maxim website (www.maxim-ic.com) for appli-
cation notes on how to choose the optimum buffer
amplifier for an ADC application. The MAX4430 is one
of the devices that is ideal for this application.
Differential Analog Input Range and
Protection
The MAX1332/MAX1333 produce a digital output that
corresponds to the differential analog input voltage as
long as the differential analog inputs are within the
specified range. When operating in unipolar mode
(BIP/
UNI
= 0), the usable differential analog input range
is from 0 to V
REF
. When operating in bipolar mode
(BIP/
UNI
= 1), the differential analog input range is from
-V
REF
/2 to +V
REF
/2. In both unipolar and bipolar
3Msps/2Msps, 5V/3V, 2-Channel, True-
Differential 12-Bit ADCs
14
______________________________________________________________________________________
CONTROL
LOGIC
CAPACITIVE
DAC
AIN_P
AIN_N
AGND
AV
DD
C
IN+
R
IN+
C
IN-
R
IN-
COMP
Figure 3b. Equivalent Input Circuit (Hold/Conversion Mode)
CONTROL
LOGIC
CAPACITIVE
DAC
AIN_P
AIN_N
AGND
AV
DD
C
IN+
R
IN+
C
IN-
R
IN-
COMP
Figure 3a. Equivalent Input Circuit (Acquisition Mode)
相關(guān)PDF資料
PDF描述
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