參數(shù)資料
型號(hào): MAX1325ECM
廠(chǎng)商: MAXIM INTEGRATED PRODUCTS INC
元件分類(lèi): ADC
英文描述: 8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs with 10V, 5V, and 0 to +5V Analog Input Ranges
中文描述: 4-CH 14-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, PQFP48
封裝: 7 X 7 MM, 1.40 MM HEIGHT, MS-026BBC, TQFP-48
文件頁(yè)數(shù): 6/27頁(yè)
文件大?。?/td> 255K
代理商: MAX1325ECM
INTEGRAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
M
DIGITAL OUTPUT CODE
I
12288
8192
4096
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0
16384
DIFFERENTIAL NONLINEARITY
vs. DIGITAL OUTPUT CODE
M
DIGITAL OUTPUT CODE
D
12288
8192
4096
-0.75
-0.50
-0.25
0
0.25
0.50
0.75
1.00
-1.00
0
16384
ANALOG SUPPLY CURRENT
vs. SUPPLY VOLTAGE
M
SUPPLY VOLTAGE (V)
S
5.12
5.00
4.87
35
40
45
50
30
4.75
5.25
f
SAMPLE
= 250ksps
ALL 8 CHANNELS
DRIVEN WITH FULL-
SCALE SINE WAVES
ANALOG SUPPLY CURRENT
vs. TEMPERATURE
M
TEMPERATURE (
°
C)
S
60
35
10
-15
35
40
45
50
30
-40
85
f
SAMPLE
=
250ksps
ALL 8 CHANNELS
DRIVEN WITH FULL-
SCALE SINE WAVES
SHUTDOWN CURRENT
vs. SUPPLY VOLTAGE
M
SUPPLY VOLTAGE (V)
S
μ
A
4.5
3.5
0.2
0.4
0.6
0.8
0
2.5
5.5
ANALOG
SHUTDOWN
CURRENT
DIGITAL
SHUTDOWN
CURRENT
SHUTDOWN CURRENT
vs. TEMPERATURE
M
TEMPERATURE (
°
C)
S
μ
A
60
35
10
-15
0.2
0.4
0.6
0.8
0
-40
85
ANALOG
SHUTDOWN
CURRENT
DIGITAL
SHUTDOWN
CURRENT
M
8-/4-/2-Channel, 14-Bit, Simultaneous-Sampling ADCs
with ±10V, ±5V, and 0 to +5V Analog Input Ranges
6
_______________________________________________________________________________________
TIMING CHARACTERISTICS (Figures 3, 4, 5, 6 and 7) (Tables 1, 3) (continued)
Note 7:
Shutdown current is measured with analog input floating. The large amplitude of the maximum shutdown current specifi-
cation is due to automatic test equipment limitations.
Defined as the change in positive full scale caused by ±5% variation in the nominal supply voltage.
CONVST must remain low for at least the acquisition period. The maximum acquisition time is limited by internal capacitor
droop.
Note 10:
CS
-to-
WR
and
CS
-to-
RD
pins are internally AND together. Setup and hold times do not apply.
Note 11:
Minimum clock frequency is limited only by the internal T/H droop rate. Limit the time between the falling edge of CONVST
to the falling edge of EOLC to a maximum of 0.25ms.
Note 12:
To avoid T/H droop degrading the sampled analog input signals, the first clock pulse should occur within 10μs of the ris-
ing edge of CONVST, and have a minimum clock frequency of 100kHz.
Note 8:
Note 9:
Typic al Operating Charac teristic s
(AV
DD
= +5V, DV
DD
= +3V, AGND = DGND = 0V, V
REF
= V
REFMS
= +2.5V (external reference), see the
Typical Operating Circuits
sec-
tion, f
CLK
= 10MHz, 50% duty cycle, INTCLK/
EXTCLK
= AGND (external clock), SHDN = DGND, T
A
= +25°C, unless otherwise noted.)
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