8-Channel, ±VREF Multirange Inputs, Serial 16-Bit ADC 6 ________________" />
參數(shù)資料
型號(hào)： MAX1302BEUG+T
廠商： Maxim Integrated Products
文件頁數(shù)： 28/31頁
文件大?。?/td> 0K
描述： IC ADC 16BIT SRL 115KSPS 24TSSOP
標(biāo)準(zhǔn)包裝： 2,500
位數(shù)： 16
采樣率（每秒）： 115k
數(shù)據(jù)接口： MICROWIRE?，QSPI?，串行，SPI?
轉(zhuǎn)換器數(shù)目： 1
功率耗散（最大）： 1.11W
電壓電源： 模擬和數(shù)字
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 24-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 24-TSSOP
包裝： 帶卷 (TR)
輸入數(shù)目和類型： 8 個(gè)單端，單極；8 個(gè)單端，雙極；4 個(gè)差分，單極；4 個(gè)差分，雙極
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
6
_______________________________________________________________________________________
ELECTRICAL CHARACTERISTICS (continued)
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, TA = -40°C to +85°C, unless otherwise noted. Typical values are at TA = +25°C.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CS Rise to DOUT Disable
tTR
40
ns
CS Fall to SCLK Rise Setup
tCSS
40
ns
CS High Minimum Pulse Width
tCSPW
40
ns
SCLK Fall to CS Rise Hold
tCSH
0ns
SSTRB Rise to CS Fall Setup
(Note 4)
40
ns
DOUT Rise/Fall Time
CL = 50pF
10
ns
SSTRB Rise/Fall Time
CL = 50pF
10
ns
Note 1: Parameter tested at VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V.
Note 2: See definitions in the
Parameter Definitions section at the end of the data sheet.
Note 3: Guaranteed by correlation with single-ended measurements.
Note 4: Not production tested. Guaranteed by design.
Note 5: To ensure external reference operation, VREFCAP must exceed (VAVDD1 - 0.1V). To ensure internal reference operation, VREFCAP
must be below (VAVDD1 - 0.4V). Bypassing REFCAP with a 0.1F or larger capacitor to AGND1 sets VREFCAP
≈ 4.096V. The tran-
sition point between internal reference mode and external reference mode lies between the REFCAP buffer disable threshold
minimum and maximum values (Figures 17 and 18).
Note 6: The SCLK duty cycle can vary between 40% and 60%, as long as the tCL and tCH timing requirements are met.
ANALOG SUPPLY CURRENT
vs. ANALOG SUPPLY VOLTAGE
MAX1302
toc01
VAVDD1 (V)
I AVDD1
(mA)
5.15
5.05
4.95
4.85
2.35
2.40
2.45
2.50
2.55
2.60
2.30
4.75
5.25
TA = +85
°C
TA = +25
°C
TA = -40
°C
EXTERNAL CLOCK MODE
PREAMPLIFIER SUPPLY CURRENT
vs. PREAMPLIFIER SUPPLY VOLTAGE
MAX1302
toc02
VAVDD2 (V)
I AVDD2
(mA)
5.15
5.05
4.85
4.95
16
17
18
19
20
21
22
23
24
15
4.75
5.25
TA = +85
°C
TA = +25
°C
TA = -40
°C
EXTERNAL CLOCK MODE
DIGITAL SUPPLY CURRENT
vs. DIGITAL SUPPLY VOLTAGE
MAX1302
toc03
VDVDD (V)
I DVDD
(mA)
5.15
5.05
4.95
4.85
0.70
0.75
0.80
0.85
0.90
0.65
4.75
5.25
TA = +85
°C
TA = +25
°C
TA = -40
°C
EXTERNAL CLOCK MODE
Typical Operating Characteristics
(VAVDD1 = VAVDD2 = VDVDD = VDVDDO = 5V, VAGND1 = VDGND = VDGNDO = VAGND2 = VAGND3 = 0V, fCLK = 3.5MHz (50% duty
cycle), external clock mode, VREF = 4.096V (external reference operation), REFCAP = AVDD1, maximum single-ended bipolar input
range (±VREF), CDOUT = 50pF, CSSTRB = 50pF, unless otherwise noted.)
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