參數(shù)資料
型號(hào): MAX1302BEUG+
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 7/31頁(yè)
文件大小: 0K
描述: IC ADC 16BIT SRL 115KSPS 24TSSOP
標(biāo)準(zhǔn)包裝: 62
位數(shù): 16
采樣率(每秒): 115k
數(shù)據(jù)接口: MICROWIRE?,QSPI?,串行,SPI?
轉(zhuǎn)換器數(shù)目: 1
功率耗散(最大): 1.11W
電壓電源: 模擬和數(shù)字
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 24-TSSOP(0.173",4.40mm 寬)
供應(yīng)商設(shè)備封裝: 24-TSSOP
包裝: 管件
輸入數(shù)目和類型: 8 個(gè)單端,單極;8 個(gè)單端,雙極;4 個(gè)差分,單極;4 個(gè)差分,雙極
As a result, the analog input impedance is relatively
constant over the input voltage as shown in Figure 5.
Single-ended conversions are internally referenced to
AGND1 (Tables 3 and 4). In differential mode, IN+ and
IN- are selected according to Tables 3 and 5. When con-
figuring differential channels, the differential pair follows
the analog configuration byte for the positive channel.
For example, to configure CH2 and CH3 for a ±VREF dif-
ferential conversion, set the CH2 analog configuration
byte for a differential conversion with the ±VREF range
(1010 1100). To initiate a conversion for the CH2 and
CH3 differential pair, issue the command 1010 0000.
Analog Input Bandwidth
The MAX1302 input-tracking circuitry has a 1.5MHz
small-signal bandwidth. The 1.5MHz input bandwidth
makes it possible to digitize high-speed transient events.
Harmonic distortion increases when digitizing signal fre-
quencies above 15kHz as shown in the -SFDR, THD vs.
Analog Input Frequency plot in the
Typical Operating
Characteristics.
Analog Input Range and Fault Tolerance
Figure 7 illustrates the software-selectable single-
ended analog input voltage range that produces a valid
digital output. Each analog input channel can be inde-
pendently programmed to one of seven single-ended
input ranges by setting the R[2:0] control bits with
DIF/SGL = 0.
MAX1302
8-Channel, ±VREF Multirange Inputs,
Serial 16-Bit ADC
______________________________________________________________________________________
15
CS
SCLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
DIN
S
C2
C1
C0
0
ANALOG INPUT
TRACK AND HOLD*
DOUT
B15
B14
B13
B12
B11
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
B0
BYTE 1
BYTE 2
BYTE 3
BYTE 4
SSTRB
HOLD
TRACK
HOLD
HIGH
IMPEDANCE
tACQ
HIGH
IMPEDANCE
*TRACK AND HOLD TIMING IS CONTROLLED BY SCLK.
fSAMPLE
≈ fSCLK / 32
SAMPLING INSTANT
Figure 2. External Clock-Mode Conversion (Mode 0)
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