參數(shù)資料
型號： MAX1288EKA-T
廠商： MAXIM INTEGRATED PRODUCTS INC
元件分類： ADC
英文描述： 150ksps, 12-Bit, 2-Channel Single-Ended, and 1-Channel True-Differential ADCs in SOT23
中文描述： 1-CH 12-BIT SUCCESSIVE APPROXIMATION ADC, SERIAL ACCESS, PDSO8
封裝： MO-178, SOT-23, 8 PIN
文件頁數(shù)： 4/15頁
文件大?。?/td> 241K
代理商： MAX1288EKA-T
M
150ksps, 12-Bit, 2-Channel S ingle-Ended, and
1-Channel True-Differential ADCs in S OT 23
4
_______________________________________________________________________________________
TIMING CHARACTERISTICS (Figures 1, 2, and 5)
(V
DD
= +2.7V to +3.6V, V
REF
= +2.5V, 0.1μF capacitor at REF, or V
DD
= +4.75V to +5.25V for MAX1286/MAX1288, V
REF
= +4.096V,
0.1μF capacitor at REF, f
SCLK
= 8MHz (50% duty cycle); AIN- = GND for MAX1288/MAX1289. T
A
= T
MIN
to T
MAX,
unless otherwise
noted. Typical values at T
A
= +25
°
C.)
PARAMETERS
SYMBOL
t
CH
t
CL
t
DOT
t
DOD
t
DOE
t
CONV
t
CSW
CONDITIONS
MIN
38
38
TYP
MAX
UNITS
ns
ns
ns
ns
ns
μs
ns
SCLK Pulse Width High
SCLK Pulse Width Low
SCLK Fall to DOUT Transition
SCLK Rise to DOUT Disable
CNVST Rise to DOUT Enable
CNVST Fall to MSB Valid
CNVST Pulse Width
C
LOAD
= 30pF
C
LOAD
= 30pF
C
LOAD
= 30pF
C
LOAD
= 30pF
60
500
80
3.7
100
30
Note 1:
Unipolar mode.
Note 2:
Relative accuracy is the deviation of the analog value at any code from its theoretical value after the full-scale range has
been calibrated.
Note 3:
Offset nulled.
Note 4:
The absolute input voltage range for the analog inputs is from GND to V
DD
.
CNVST
SCLK
DOUT
t
DOE
HIGH-Z
HIGH-Z
t
CSW
t
CL
t
CH
t
DOD
t
DOT
DOUT
6k
6k
C
L
GND
DOUT
C
L
GND
V
DD
a) HIGH -Z TOV
OH
, V
OL
TOV
OH
, AND V
OH
TOHIGH -Z
b) HIGH -Z TOV
OL
, V
OH
TOV
OL
, AND V
OL
TOHIGH -Z
Figure 1. Detailed Serial-Interface Timing Sequence
Figure 2. Load Circuits for Enable/Disable Times
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