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參數(shù)資料
| 型號： | MAX1184ECM+TD |
| 廠商： | Maxim Integrated Products |
| 文件頁數(shù)： | 17/21頁 |
| 文件大小： | 0K |
| 描述： | IC ADC 10BIT 20MSPS DL 48-TQFP |
| 產(chǎn)品培訓(xùn)模塊： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 標(biāo)準(zhǔn)包裝： | 2,000 |
| 位數(shù)： | 10 |
| 采樣率（每秒）： | 20M |
| 數(shù)據(jù)接口： | 并聯(lián) |
| 轉(zhuǎn)換器數(shù)目： | 2 |
| 功率耗散（最大）： | 150mW |
| 電壓電源： | 單電源 |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-TQFP 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-TQFP 裸露焊盤（7x7） |
| 包裝： | 帶卷 (TR) |
| 輸入數(shù)目和類型： | 4 個單端，雙極；2 個差分，雙極 |
MAX1184
Dual 10-Bit, 20Msps, 3V, Low-Power ADC with
Internal Reference and Parallel Outputs
_______________________________________________________________________________________
5
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3V, OVDD = 2.5V, 0.1F and 1.0F capacitors from REFP, REFN, and COM to GND; REFOUT connected to REFIN through a
10k
resistor, VIN = 2VP-P (differential with respect to. COM), CL = 10pF at digital outputs (Note 1), fCLK = 20MHz, TA = TMIN to
TMAX, unless otherwise noted. Typical values are at TA = +25°C.) (Note 2)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
POWER REQUIREMENTS
Analog Supply Voltage Range
VDD
2.7
3.0
3.6
V
Output Supply Voltage Range
OVDD
1.7
2.5
3.6
V
Operating, fINA or B = 7.5MHz at -0.5dBFS
35
50
Sleep mode
2.8
mA
Analog Supply Current
IVDD
Shutdown, clock idle, PD =
OE = OVDD
115
A
Operating, CL = 15pF, fINA or B = 7.5MHz at
-0.5dBFS
3.8
mA
Sleep mode
100
Output Supply Current
IOVDD
Shutdown, clock idle, PD =
OE = OVDD
210
A
Operating, fINA or B = 7.5MHz at -0.5dBFS
105
150
Sleep mode
8.4
mW
Power Dissipation
PDISS
Shutdown, clock idle, PD =
OE = OVDD
345
W
Offset
±0.2
mV/V
Power-Supply Rejection Ratio
PSRR
Gain
±0.1
%/V
TIMING CHARACTERISTICS
CLK Rise to Output Data Valid
tDO
Figure 3 (Note 5)
5
8
ns
Output Enable Time
tENABLE
Figure 4
10
ns
Output Disable Time
tDISABLE
Figure 4
1.5
ns
CLK Pulse Width High
tCH
Figure 3, clock period: 50ns
25
± 7.5
ns
CLK Pulse Width Low
tCL
Figure 3, clock period: 50ns
25
± 7.5
ns
Wake up from sleep mode (Note 6)
0.51
Wake-Up Time
tWAKE
Wake up from shutdown (Note 6)
1.5
s
CHANNEL-TO-CHANNEL MATCHING
Crosstalk
fINA or B = 7.5MHz at -0.5dBFS
-70
dB
Gain Matching
fINA or B = 7.5MHz at -0.5dBFS
0.02
±0.2
dB
Phase Matching
fINA or B = 7.5MHz at -0.5dBFS
0.25
degrees
Note 1: Equivalent dynamic performance is obtainable over full OVDD range with reduced CL.
Note 2: Specifications at
≥ +25°C are guaranteed by production test and < +25°C are guaranteed by design and characterization.
Note 3: SNR, SINAD, THD, SFDR, and HD3 are based on an analog input voltage of -0.5dBFS referenced to a 1.024V full-scale
input voltage range.
Note 4: Intermodulation distortion is the total power of the intermodulation products relative to the individual carrier. This number is
6dB or better, if referenced to the two-tone envelope.
Note 5: Digital outputs settle to VIH, VIL. Parameter guaranteed by design.
Note 6: With REFIN driven externally, REFP, COM, and REFN are left floating while powered down.
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