Controllers with I2C/SP" />
參數(shù)資料
型號(hào): MAX11802EWC+T
廠商: Maxim Integrated Products
文件頁(yè)數(shù): 48/59頁(yè)
文件大?。?/td> 0K
描述: IC TOUCH SCREEN CTLR 12-WLP
產(chǎn)品培訓(xùn)模塊: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
標(biāo)準(zhǔn)包裝: 1
類型: 電阻
觸摸面板接口: 4 線
輸入數(shù)/鍵: 1 TSC
分辨率(位): 12 b
數(shù)據(jù)接口: 串行,SPI?
數(shù)據(jù)速率/采樣率 (SPS,BPS): 105k
電源電壓: 1.7 V ~ 3.6 V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 12-WFBGA,WLCSP
供應(yīng)商設(shè)備封裝: 12-WLP
包裝: 標(biāo)準(zhǔn)包裝
其它名稱: MAX11802EWC+TDKR
MAX11800–MAX11803
Low-Power, Ultra-Small Resistive Touch-Screen
Controllers with I2C/SPI Interface
52
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Note: These settings apply to measurement commands, combined commands, and autonomous conversion mode measurements
and provide time for the panel to settle prior to beginning measurements. During these periods, the panel is set up, but the ADC
remains powered down. Users with low-impedance/fast settling panels should use setting 0000 (skip mode) if their panel can be set-
tled during the required 10μs minimum delayed conversion time (see the Delayed Conversion Configuration Register (0x06) section).
BIT
7
6
5
4
3
2
1
0
NAME
D_CV_XY[3:0]
D_CV_Z[3:0]
DEFAULT
0
BIT
NAME
DESCRIPTION
MAX11800/
MAX11801
MAX11802/
MAX11803
7:4
D_CV_XY[3:0]
X, Y panel plus ADC setup times (position measurements)
0000: 10μs
1000: 1ms
0001: 20μs
1001: 2ms
0010: 50μs
1010: 5ms
0011: 80μs
1011: 10ms
0100: 100μs
1100: 20ms
0101: 200μs
1101: 50ms
0110: 500μs
1110: 100ms
0111: 800μs
1111: 200ms
Yes
3:0
D_CV_Z[3:0]
Z panel plus ADC setup times (pressure measurements)
D_CV_Z[3:0] has the same range as D_CV_XY[3:0] above.
Yes
Delayed Conversion Configuration Register (0x06)
Note: These settings apply to measurement commands, combined commands, and autonomous conversion mode measurements
and provide time for the panel and ADC to settle prior to beginning measurements. During these periods, the panel is set up and the
ADC is powered up. In general, users with long panel settling requirements should minimize time in this mode, using increased
panel setup times instead to save ADC power.
BIT
7
6
5
4
3
2
1
0
NAME
PSUXY[3:0]
PSUZ[3:0]
DEFAULT
0
BIT
NAME
DESCRIPTION
MAX11800/
MAX11801
MAX11802/
MAX11803
7:4
PSUXY[3:0]
X, Y panel setup times (position measurements)
0000: 0μs
1000: 1ms
0001: 20μs
1001: 2ms
0010: 50μs
1010: 5ms
0011: 80μs
1011: 10ms
0100: 100μs
1100: 20ms
0101: 200μs
1101: 50ms
0110: 500μs
1110: 100ms
0111: 800μs
1111: 200ms
Yes
3:0
PSUZ[3:0]
Z panel setup times (pressure measurements)
PSUZ[3:0] has the same range as PSUXY[3:0] above.
Yes
Panel Setup Timing Configuration Register (0x05)
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